2D Packaging with Direct Bonded Circuit (DBC) Technology

Get Complete Project Material File(s) Now! »

Thermal Management Solutions

As mentioned previously, with the increase of power densities and harsh operating environments, thermal management becomes more and more a central issue in power electronics. For example, “the heat flux of power electronic device for hybrid electric vehicles is currently at the level of 100-200 W/cm2 and is projected to increase up to 500 W/cm2 in next generation vehicles” [117]. This kind of high heat fluxes will bring us higher but less uniform junction temperature of the chip, which is a critical issue of degrading the performance and reliability of power systems.
So as shown in Fig.1-24 [118], the objective of thermal management is to control the junction temperature of power components to avoid thermal fatigue, short lifetime and irreversible destruction. The main efforts have to be focused on minimizing overall thermal resistance of the power electronics systems. Most cooling technologies rely on heat spreading and convection.
Here in this part, conventional concepts as air cooling, liquid cooling, as well as cooling by thermal vias are reviewed and recent concepts as thermoelectric cooling and hybrid cooling by Peltier modules are described. Their advantages and disadvantages will be given and compared.

Solid Cooling

Conventional assemblies used in industrial applications based on standard modules with air cooled aluminum heat sinks are too heavy and voluminous, especially for automotive uses. Besides, the heat conduction capability of the cooling system or the thermal path of the structure is always the dominant factor of its thermal performances. So many efforts such as developing new semiconductor materials with higher thermal conductivities or improving packaging technologies, have been contributed in order to reduce the thermal resistances of the total structure with less additional components.
Recently, besides traditional solid-technologies of thermal vias, advanced thermoelectric solid-state cooling technology, based on polycrystalline miniaturized TE cooler [128], nanostructured superlattice TEC [129], mini-contact enhancement technology [130], and silicon and germanium substrate self-cooling [131] have received great attention and considerable progress has been made at the research level for high flux thermal management for microprocessors and electro-optic components. These solid-state techniques have compact structure, offer high reliability, can be locally applied, provide high cooling flux, and can be integrated with IC processing.
A thermal via is a plated through hole (PTH) plated with copper and is used to transfer the heat from one side of the PCB to the other side. PTH is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the structure. With thermal vias, the PCB acts as a pathway for the heat energy to reach the main heatsink, rather than serving as the heatsink itself. For example, main heat transfer path for a 2 layer PCB with thermal vias is shown in the Fig.1-28 [132].

Applied Softwares

The main methods used for thermal performances analysis are analytical (2D) and 3D FE methods. On the one hand, analytical methods are based on thermal theories as heat convection, heat conduction and heat radiation. Analytical models will be created with the help of Matlab Simulink. On the other hand, 3D FEM is a numerical method allowing to solve problems in some area of physics as for simulation of dielectric, magnetic, thermal, mechanic etc. Here in this thesis, software COMSOL Multiphysics has been used mainly for 3D thermal simulations.
This part is devoted to introduce the modelling process with the two softwares (Matlab, COMSOL) in case of a simple PCB structure shown in Fig.2-8 (a). The structure dimensions are shown in Fig.2-10. The purpose is to estimate the maximum chip temperature Tc (℃). Power of 1 W is input in the chip for all simulations. Heat convection and heat radiation effect have been neglected to simplify the simulations here.

CHIP ATTACHMENT ON THE PCB SUBSTRATE

This part mainly focuses on the fabrication technology of PCB structure. Based on a soldering procedure of Si chip on the PCB substrate, preparation process of PCB as well as the realization of the chip attachment will be presented in order to introduce the materials and equipments used for manufacturing a PCB structure.

READ  Polarimetric Massive MIMO Channel Measurements in an Industry 4.0 

Preparation of PCB Substrate

A full fabrication process of PCB is shown in Fig.2-14 [161]. The typical processes to prepare the PCB substrate as shown in Fig.2-15 are described in the following five steps:
 Step 1: Creating the substrate by lamination technology with prepreg, which is a glass fabric pre-impregnated in resin. More details could be found in [161].
 Step 2: Substrate cleaning. Before covering the substrate by resin or photosensitive film, this cleaning step is important to avoid yielding a poor coating by the resin. That means, the particles or the residues left on the surface may create small holes in the deposited layer.
 Step 3: Photolithography. Firstly, coating or marking the substrate with liquid photoresist which aims to protect the copper part of the circuit. Then it is exposed to an ultraviolet radiation so that the exposed areas become soluble for positive resin. Here the etch mask with ink pattern can be created by Eagle or Altium softwares. Lastly, the development step is realized by dipping the PCB substrate in a developer. The exposed area of the photoresist will be dissolved for the positive resin.
 Step 4: Etching. The copper etching is made directly in ferric chloride solution or with an etchant spray system. And it’s necessary to do this step repeatedly until the exposed copper part is fully cleaned.
 Step 5: Stripping. This last step is to clean the substrate with chemical reagent before the chip soldering.
More details of applied materials and fabrication technologies of PCB are described in the thesis of YU [2].

Table of contents :

Résumé en français
List of figures
List of tables
General Introduction
CHAPTER 1. State of The Art
1.1. Introduction
1.2. Power Converters
1.2.1. Semiconductor Components
1.2.2. Multilevel Converters
1.3. Power Packaging
1.3.1. Introduction
1.3.2. 2D Packaging with Direct Bonded Circuit (DBC) Technology
1.3.3. 3D Packaging with Printed Circuit Board (PCB) Technology
1.3.4. Conclusion
1.4. Thermal Analysis of Power Electronics Systems
1.4.1. Introduction
1.4.2. Thermal Measurement Methods
1.4.3. Thermal Management Solutions
1.5. Summary
CHAPTER 2. Thermal Instrumentations
2.1. Introduction
2.2. Test Bench
2.2.1. Establishment
2.2.2. RTD Sensor (PT 100) Calibration
2.2.3. Thermal Conductivity of Duralumin 𝜆dura (W/mK)
2.2.4. Temperature Measurement Equipments
2.2.5. Applied Softwares
2.3. Chip Attachment on The PCB Substrate
2.3.1. Preparation of PCB Substrate
2.3.2. Chip Soldering
2.4. Through-Hole Electroplating
2.5. Summary
CHAPTER 3. Optimization of thermal vias
3.1. Introduction
3.2. Analytical Analysis
3.2.1. PCB Substrate with One Individual Thermal Via
3.2.2. PCB Substrate with Two Thermal Vias
3.2.3. PCB Substrate with Multiple Vias
3.3. 3D FEM Analysis
3.3.1. Number of Thermal Vias N
3.3.2. Via-Cluster Surface Ratio Ro1
3.3.3. Via Diameter Ratio Ro2
3.3.4. Via Plating Thickness Ratio Ro3
3.3.5. Via Pattern
3.3.6. Copper Thickness on The PCB Substrate
3.4. Experimental Results and Discussions
3.5. Conception of The Inverse Thermal Model
3.5.1. Introduction
3.5.2. Steady State Inverse Heat Conduction Model (IHCM)
3.5.3. Dissipated Power Prediction
3.5.4. Dissipated Power and Thermal Conductivity Prediction
3.6. Summary
CHAPTER 4. Thermoelectric Cooling
4.1. Introduction
4.2. 3D FEM Analysis
4.2.1. Placement of The Peltier Device dgp and Number of Peltier Elements Np
4.2.2. Copper Thickness on The PCB Substrate
4.2.3. Modeling of The Peltier Device CP39236H
4.3. 1D Electro-Thermal Modeling
4.3.1. 1D Modeling of The Cooling Structure
4.3.2. 1D and 3D Simulation Results and Discussions
4.4. Experimental Validation
4.4.1. Test Bench
4.4.2. Results and Discussions
4.4.3. Influences of Number of Peltier Elements N
4.5. Summary
Conclusions and Perspectives
References
Annex A
Annex B
Annex C
Annex D

GET THE COMPLETE PROJECT

Related Posts