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Silicon carbide (SiC)

Silicon carbide, as was first discovered by Jons Jakob Berzelius in 1824 [4], is one of the attractive semiconductors for high temperature, high power, and high frequency appli-cation [5]. The commercial value of SiC has been discovered early days such as abrasive, high-temperature ceramics and fireproofing thanks to its advantages in either hardness or melting characteristics [6]. Soon it has emerged as the most mature of the wide-bandgap semiconductors since the release of commercial 6H-SiC bulk substrates in 1991 and 4H-SiC substrates in 1994 [7]. As is shown in Table 1.1, SiC is superior to Si especially for power device application due to its large bandgap, high breakdown field and high thermal conductivity. As a result, the SiC devices can benefit from higher blocking voltage, lower on-resistance, reduced leakage current and higher operation temperature/frequency com-pared to that made by Si. Therefore, silicon carbide is an ideal alternative to silicon for de-vices over 10 kV, as shown in Figure 1.2. A great deal of SiC devices with ultra-high breakdown voltage have been reported such as 15~20 kV 4H-SiC IGBTs [8] and 20 kV 4H-SiC gate turn-off thyristors [9].
The crystal lattice of SiC is recognized as closely packed silicon-carbon bilayers (or Si-C double layers), which can be regarded as the alternately arranged planar sheets of sil-icon or carbon atoms. Due to the variation of stacking sequences, different polytypes can be presented. Among over 150 polytypes found in SiC, however, only the 6H- and 4H-SiC polytypes are commercially available in both bulk wafers and custom epitaxial layers. Be-tween the two polytypes, 4H-SiC is preferred for power devices primarily because of its high carrier mobility, particularly in c-axis direction and its low dopant ionization energy [12].
Apart from those breakthroughs reported from the laboratories, as listed in Table 1.2, lots of commercial SiC power devices are now available on thousand volt class with re-duced on-resistance compared to Si devices. With the development on breakthrough of SiC wafer fabrication and maturity of the process, SiC devices will continue to expend their influences in power field.

Schottky barrier diodes (SBD)

SiC p-n junctions could suffer a higher forward power loss compared to Si due to its higher built-in voltage. However, this can be avoided by a Schottky structure [14]. Nowa-days, the 4H-SiC Schottky-barrier diodes (SBDs) have already shown much attraction in power systems because of their low conduction loss, fast switching speed and high operat-ing temperature [15]. Junction Barrier Schottky (JBS) diode is another significant family of SiC power devices which consist of an interconnected grid of p-type regions in the n-type drift layer. As a result, JBS combine the advantages of both SBD and PiN diode and are wildly used in various fields such as power supplies, aerospace power systems, high-performance communication systems, and power conversion systems [16].
Both the electric and dielectric properties of the Schottky Barrier Diodes (SBDs) are dependent on various factors. The most effective of them among interface states are the impurity, the thickness and homogeneity of interfacial layer and barrier height (BH) at M/S interface [17].

Multi-barrier in SBD

During the characterization of Shottky diodes in our laboratory, a double barrier phe-nomenon has been discovered, which can be identified as abnormal high current under low forward bias, as is shown in Figure 1.3. This has shown up not only among different met-als such as Ni, Ti/W, Mo, but also in various metal processes like sputtering or lift-off.
Similar phenomenons have been reported, and it was highlighted that these ‘non-ideal’ diodes occurred regardless of growth technique, pre-deposition cleaning method, or con-tact metal [18]. Moreover, this double barrier was found to be more common at lower temperature, as shown in Figure 1.4, which was explained by barrier height inhomogenei-ties [19].
As widely reported, the multi-barrier phenomenon should have an origin in common, and those invisible deep levels that can greatly influence the device performance are one of the most possible contributions to this.

Reliability and Defects

Defects and impurities in semiconducting materials can result in poorer property such as a carrier lifetime reduction [20]. Especially those deep level defects, which are close to midgap, can be efficient recombination centers or carrier traps. Meanwhile, charged inter-face traps directly affect the device performance by increasing the threshold voltage, de-grading the channel mobility and causing leakage current for MOS applications [21]. On the other hand, trap levels can be sometimes important for carrier lifetime adjustment as well as in the application of LEDs. These deep level defects can not only be caused by ir-radiation [22] or impurities such as Ti, V, Cr [23] but also be intrinsic defects introduced by manufacturing process such as carbon vacancy (VC) [24, 25]. Activation Energy ( Ea ), capture cross section ( ) and defect concentration ( NT ) are all significant parameters for deep level defects identification.

Classification of defects

Forms of defects

According to different forms in semiconductor, defects can be simply classified as point defects and extended defects, while extended defects includes various of defect types based on their dimension and characteristics, one example is listed in Table 1.3.
Some common defects are explained as follows:
 Vacancies
A vacancy, one of the simplest point defect also known as a Schottky defect [26], comes from the absence of an atom in the lattice [27], while the missing usually takes place in pairs in those ionic crystals (e.g. the alkali halide crystals) to maintain charge bal-ance [28]. Irradiation is regarded as a common way to introduce vacancies by using vari-ous particles (electrons, protons, neutron or even He+) with wide energy range [29-32], and part of them can be annealed at high temperature [33-35]. On the other hand, secondary defects can be produced after annealing at 400 ℃ [35] and the agglomeration of defects to larger vacancy complexes has been reported as well [36, 37].
 Substitutional defects
Substitutional defects stand for the replacement of original atom by an impurity such as the doping process of semiconductor that usually contributes to introducing shallow levels in the bandgap. This normally refers to those atoms of either original ones or impu-rities that have the comparable size (e.g. N or Al in SiC or Si), otherwise the interstitial de-fects will be formed.
 Interstitial and Frenkel defects
If the gap of lattice is occupied where no atom should exist, this type of defect is known as interstitial. Another possibility is the share of one lattice site by two or more at-oms. Frenkel defects can be regarded as the combination of both an interstitial atom and related vacancies caused by lattice atoms.
 Dislocations
As a common example of extended defects, dislocation stands for the bending of at-om planes surrounding due to the termination of the atom plane in the crystal. It was first put forward by Volterra in 1970 [38], and can be classified as screw dislocation or edge dislocation according to different types. By studying the dislocations parallel to the Schottky contact, FIGIELS has discussed that the kinetics of electron emission from dislo-cation will be drastically modified due to the configuration entropy. As a consequence, the Deep Level Transient Spectroscopy (DLTS) transients no longer follow the exponential law and results in the broadening of DLTS signal [39].
 Stacking faults
Stacking faults refer to the locally changed stacking order of atom layer(s) in the structure. For example, instead of the typical stacking sequence ABCABCABC of face-centered cubic (fcc) structure, the structure with stacking fault may be ABCABABCAB. Furthermore, the correlation between stacking faults and double barrier phenomenon has been reported [40].
 Surface defects
Teng ZHANG / Thèse en Génie électrique / 2018 / Institut national des sciences appliquées de Lyon tous droits réservés Surface defect is another significant category of defect. Generally speaking, surface defects do not refer to the specific defect type as discussed before, but focus on the posi-tion where large fraction of dialing bond occur and the periodic of lattice is destroyed. As a result, the carrier lifetime, mobility etc. can be affected near the surface. In addition, sim-ilar defects can lie in the interface between semiconductor and metal/oxide and is recog-nized as interface states, which can be the decisive factor of Schottky barrier height under certain circumstance instead of the metal type.

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Shallow and deep levels

Apart from the classification of defects according to their forms or crystal condition, defects can also be classified as shallow or deep defects based on the location of their en-ergy levels in the bandgap of the semiconductor. A defect level is regarded as shallow lev-el if its energy level is located near the band edges (conduction or valence band) of the semiconductor. One of the most common shallow levels is those impurities introduced by doping, which directly modifies the electrical properties (conductivity, carrier mobility etc.) of the semiconductors. In addition to impurities that usually take place as substitutions, the interstitial atoms that contribute to shallow levels have been reported as well [41, 42].
On the other hand, generally the deep levels have less contribution to conduction compared with the shallow levels of dopants due to their relatively low concentration and large activation energy. However, these deep levels can play an important role in the re-combination process and are regarded as a significant limitation on carrier lifetime espe-cially when the energy levels lie near the middle of the bandgap. As one of the applica-tions, it is possible to release the carrier storage effect by limiting carrier life time with the help of recombination center introduced by Au impurities in silicon devices, since Au is known as a lifetime killer in silicon [43].

Defects reported in SiC devices

Since 1990s, a great deal of researches about deep level defects in SiC has been done with the help of DLTS or other investigation methods. The donor deep levels with almost full range of activation energy have been reported, as is shown in Figure 1.5. Obviously, these deep levels focus on activation energy from 0.1 eV to 0.9 eV, including the well-known Z1/2 defect with Ea around 0.68 eV.
Various of impurity defects have been investigated by means of doping or implanta-tion [44, 45], part of them found in 4H-SiC are illustrated in Table 1.4. Other impurity de-fects such as O and Er have been reported in 6H-SiC [46, 47].
Recently, more attention has been payed on characteristic of deep level defects and its relation to device properties. Danno and Kimoto have pointed out the similarity between Z1/2 and EH6/7 (with Ea around 1.6 eV) due to the fact that the concentration of Z1/2 and EH6/7 have the same trend regardless of As-growth, irradiation or annealing. They believe both centers contain the same defect such as a carbon vacancy [48]. As the two dominant electron traps, Z1/2 and EH6/7 could both survive after high temperature annealing at 1700 ℃ [49]. However, Klein argued that Z1/2 acted alone as the lifetime limiting defect [50]. By comparing the concentration of carbon vacancy (VC) determined by electron paramagnetic resonance with that of Z1/2 defect obtained by C-V and DLTS, Kawahara argued that the Z1/2 originates from VC [51], similar conclusion has been drawn in [52].
Meanwhile, several effects have been put forward as
 Poole-Frenkel Effect: The strong electric field close to the metal-semiconductor interface enhances the emission rate by lowering the potential barrier over which the carrier is thermally emitted. Therefore, increased applied electric field should lead to lower activation energy [53].
 Carrier Freeze-out Effect: Strong compensation of the dopant and the high con-centration of radiation-induced defects takes place at low temperature [54].
 Lambda Effect ( Effect): When measuring the deep levels in semiconductor diodes, the transition zone near the edge of the space charge region (SCR) owing to the extended Debye tail of free carriers from the neutral material should be taken into consideration. Particularly, this width of correction should be further modified in non-steady state [55].
In addition, certain traps are invisible to the measurements that should be paid atten-tion as well. In particular, in the certain region near surface, electrons are not captured by the traps during the filling pulse. Whereas near the opposite edge of a depletion layer, electrons in the deep level located below the Fermi level even when the reverse bias is applied can be always trapped without emission [56].
On the other hand, the correlation between the observation of the two barrier height behavior in the I-V characteristics and traps measured from DLTS and Random Telegraph Signal (RTS) dates back to year 2002 [57]. It was pointed out that the I-V characteristics tended to degrade with increasing deep-level concentration and those inhomogeneous di-odes tended to contain defect clusters, which can lead to a local Fermi-level pinning [18]. Gelczuk also argued that traps partially are responsible for the observed barrier height in-homogeneities [19].

Table of contents :

1.1 Background
1.1.1 Development of modern power electronics and its limitation
1.1.2 Silicon carbide (SiC)
1.1.3 Schottky barrier diodes (SBD)
1.1.4 Multi-barrier in SBD
1.2 Reliability and Defects
1.2.1 Classification of defects
1.2.2 Defects reported in SiC devices
2.1 Energy band diagram and formation of Schottky barrier diode
2.1.1 Ideal Schottky contact
2.1.2 The effect of interface states
2.2 Current transport mechanisms though Schottky barrier
2.2.1 Introduction
2.2.2 The diffusion theory
2.2.3 The thermionic-emission (TE) theory
2.2.4 Tunneling and Thermionic-Field Emission (TFE) model
2.2.5 Recombination in the depletion region
2.2.6 Image-force lowering of SBH
2.3 Measurement of SBH
2.3.1 I-V characteristics
2.3.2 C-V measurements
2.4 Review on SBH models
2.4.1 Ideality factor and zero-bias barrier height
2.4.2 T0 effect
2.4.3 Gaussian distribution
2.4.4 Potential Fluctuation model
2.4.5 Flat-band barrier height
2.4.6 Modified Richardson plot
2.4.7 Relationships between different models
2.5 Barrier inhomogeneity in Schottky devices
2.5.1 Introduction
2.5.2 Parallel diode model
2.5.3 Tung’s model
2.5.4 Multi Gaussian distribution model
3.1 Overview
3.2 Electron capture-emission mechanism
3.2.1 Capture
3.2.2 Emission
3.2.3 Steady state capture-emission
3.2.4 Transient
3.2.5 Limitation on trap detection
3.3 DLTS Principle
3.3.1 Basic DLTS principle
3.3.2 Fourier transform and DLTFS
3.4 Category of DLTS
3.4.1 DLTS transient modes
3.4.2 Isothermal DLTS
3.4.3 Other DLTS
4.1 Sample used in this study
4.1.1 Overview
4.1.2 Preliminary statistics
4.2 Measurements setup
4.2.1 Hardware setup
4.2.2 I-V measurements
4.2.3 C-V measurements
4.2.4 DLTS measurement
4.3 Experimental results
4.3.1 Case study: Ti/W liftoff sample
4.3.2 Research on diode with multi-barriers
4.3.3 Comparison on samples with different metal contacts
5.1 PiN diode
5.1.1 Sample overview
5.1.2 Experiment setup
5.1.3 Static Characterization
5.1.4 DLTS characterization
5.2.1 Introduction
5.2.2 Experiments setup
5.2.3 Experimental results
5.2.4 Discussion
5.3 Discussion
5.3.1 Freeze-out effect
5.3.2 Relationship between activation energy and capture cross section of certain defect level
5.3.3 Annealing effect during DLTS
5.3.4 Negative-U center
5.3.5 Behavior at extremely low temperature
6.1 Conclusion
6.2 Perspective


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