The critical case of inter-gate coupling is called “super-coupling” effect . The super- coupling effect dictates that only one type of mobile carriers can be accommodated in an ultrathin silicon body. The limit for the silicon thickness where the supercoupling is revealed or not is known as critical thickness, tSi* , , . If the silicon film thickness (tSi) is thinner than the critical thickness, i.e. tSi <tSi*, the potential drop across the body is insufficient to sustain both carriers simultaneously. Namely, the body acts like a quasi-rigid potential well where one of the gates prevails. Figure 1.16 shows thick-body and ultrathin body SOI transistors. For the thick-body device (Fig. 1.16a), electrons and holes can co-exist in the body. However, for ultrathin device, the supercoupling inhibits the presence of both carriers.
Threshold Voltage Coupling
The supercoupling effect is examined by evaluation the threshold voltage variation with the back-gate bias. Figure 1.19 shows the simulated results, depending on several film thicknesses from 10 nm to 5 nm. For tSi = 10 nm film (Fig. 1.19a), the front threshold voltage (VTf) varies from 2 V to -5 V and then it saturates beyond the VGb = -5 V. A plateau region is observed because of the presence of an accumulation holes layer at the back-interface; i.e. inter-gate coupling stops. The plateau appears for VGb more negative in thinner silicon films as demonstrated in Figure 1.19b, c. The enhancement of electrostatic control is accomplished by thinning the silicon thickness. For a short channel device (LG = 20 nm) on tSi = 10 nm (Fig. 1.19a), this curve deviates from the long channel coupling curves, due to the SCE. In an ultrathin body (tSi = 5 nm), however, the lateral encroachment from drain is well controlled. The saturation region tends to disappear, therefore reducing the SCE . In a practical point of view, the back-gate control can be applicable even for voltages lower than -6 V in the ultrathin body (< 10 nm) and BOX (> 10 nm).
Figure 1.19d shows the front body factor (or front-to-back gate coupling ratio) versus the gate length. When the body thickness is much thinner than the gate length (LG), the gate coupling ratio is very high and shows little variation with LG. This implies that the front-gate bias is stronger thanks to the thinner body. In thicker films, the SCEs make the coupling coefficient to decrease dramatically.
Short channel Effects in FDSOI
In modern electronic industries based on VLSI circuits, the device scaling is the most substantial factor to enhance device performances such as high-speed operation, low-power consumption, and increasing integration density. To achieve all of that, the critical dimensions of MOSFETs have to be shrunk physically. Reducing the channel length is a simple way to meet the requirement but the short-channel effects (SCE) must be considered completely. The performances of MOSFET devices are related to the electrostatic control of the channel by the gate.
In general, for the nanoscale VLSI circuit design, the effective channel length influences the device characteristics related to the SCEs such as subthreshold slope degradation and drain-induced barrier lowering (DIBL). It is obvious that the SCEs are originated by the encroachment of the electric field from the terminals, i.e. source and drain, into the effective channel region underneath the gate. This encroachment leads to competition for the control of the available depletion area underneath the gate, thereby decreasing the threshold voltage. When the drain voltage is high enough, the surface potential in the channel and inversion electrons are no longer controlled by the gate bias. The lateral depletion width (Wd) of source and drain is given by Equation 1.12  with source bias (VS), drain bias (VD), and built-in potential barrier (Vbi): Wd S, D Si∙ D( bi S, D) ∙ A( D A) (1.12).
No matter what novel technologies are used for device integration, this depletion width has to be minimized. Less influence from the lateral encroachment yields good immunity against the main SCE: threshold voltage roll-off (due to shared depletion charges) and drain induced barrier lowering (DIBL).
In FDSOI MOSFETs, especially, the SCE is inherently mitigated by the shallow silicon thickness but it is not perfectly diminished due to the source and drain electric field, i.e. 2-D effects , , , . The latter matter thus has to be considered and solved even for ultrathin FDSOI MOSFETs. Regarding the reduction of the SCE, a viable approach is used to the multi-gate architectures discussed in section 1.2.2.
Compound Semiconductor on Insulator Devices
Semiconductor on Insulator (SOI) is a generic term describing the various CMOS applications. Among those, boosting the carrier mobility is a valuable approach to enhance device performance without side effects. This is because current density is proportional to the carrier mobility. There are many possible solutions to get high-mobility channels such as Ge, strained silicon (SiGe), and all III-V compounds materials for advanced high-speed devices , . Figure 1.22 shows the process flow for III-V-on-Insulator wafers fabricated by IBM Zurich Research Laboratory. Direct wafer bonding (DWB) is used to prepare large-scale wafers before processing the ultrathin III-V-OI devices.
The III-V compound semiconductors are now taken into account for mainstream research in order to extend the CMOS technology roadmap beyond the 14 nm node. In particular, it is envisioned that In(x)Ga(1-x)As(x ≥ 0.53) n-MOSFETs will be coupled to (Si)Ge p-MOSFETs to deliver an optimum electron/hole performance while leveraging the wide industry experience with SiGe. The potential benefits of InGaAs-based nMOSFETs have already been demonstrated –.
Kink Effect in Ultrathin Fully-Depleted SOI MOSFETs
The kink effect is defined by the appearance of non-linear behavior in the output characteristics of a SOI MOSFET as demonstrated in Figure 2.1 , .
This effect is quite pronounced in partially-depleted (PD) SOI MOSFETs. Majority carriers are generated by impact ionization and stored within the neutral region. As a result, the body potential begins to increase and then lowers the threshold voltage progressively , –. Since more carriers are available in the channel, the impact ionization process is amplified, which further increases the body potential. This positive feedback mechanism results in a sudden increase in drain current that can be beneficial for current drive and speed in logic circuits as the current over-driver circuitry in the conventional DRAM. It is, however, detrimental for the linearity of analog circuits.
We revisit the presence of the kink effect systematically in ultrathin FDSOI MOSFETs fabricated by CEA-Leti or STMicroelectronics for 28 nm node technology. The back-gate bias enables to control the kink effect via the formation of an accumulation holes layer at the back interface. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (< 10 nm) and/or very short transistors (L < 50 nm), the kink is entirely absent as a consequence of super-coupling effect.
Generally speaking, the kink effect has also been observed in relatively thick fully depleted (FD) SOI MOSFETs, where the back gate was used to convert FD operation into PD mode . A negative back-gate voltage enabled the storage of enough holes near the back Si-BOX interface, thereby triggering the kink behavior of output characteristics , . In the following sub-section, experimental results and TCAD simulations are demonstrated for verifying the kink effect in FDSOI devices. We show up-to-date recent data about the kink effect:
– The experimental conditions enabling the activation of the kink effect in state-of-the-art n-channel FDSOI MOSFETs with the thickness from 25 nm to 8 nm are investigated (2.2.2.).
– The body potential variation is monitored and then correlated to the drain current characteristics in order to interpret the onset of the kink effect.
– Pulsed measurements are performed in order to confirm the impact of the generation rate of majority carriers on the kink effect during a designated pulse period and width (2.2.3.).
– TCAD device simulation is conducted (2.2.4.) that guides us to interpret the variation of the kink effect.
Gate-Induced FBE (GIFBE) in Ultrathin MOSFETs
In FDSOI MOSFETs with thin gate dielectric (< 2 nm), the body can be charged by occurring the gate tunneling current. The direct tunneling of electrons from the valence band of silicon film into the gate leaves excess holes in the body , . The excess holes increase the body potential, which is reducing the threshold voltage. Consequently, the subsequent lowering of the threshold voltage boosts the drain current and gives rise to a second peak in transconductance as demonstrated in Figure 2.25 . This mechanism is called gate-induced floating body effect, GIFBE. The first report on GIFBE was for partially depleted SOI MOSFETs, about 20 years ago .
The body-contact FDSOI MOSFETs, combining three different silicon films and few gate lengths, are examined systematically (Table. 2.2). This work represents experimental results for the GIFBE in recent FDSOI MOSFETs.
Figure 2.25: Transconductance vs. front-gate voltage in FDSOI n-MOSFET showing the impact of GIFBE. tox = 1.6 nm, tSi = 17 nm, tBOX = 145 nm, VD = 0.1 V .
Current and Transconductance Characteristics
We show the band diagram for explaining the basic mechanism of GIFBE. The tungsten metal gate, silicon dioxide, p-type silicon body, and buried oxide (BOX) layers are illustrated in separated columns in Figure 2.26a. After becoming one system, the Fermi level is completely flat in Figure 2.26b. When a depletion layer (or weak accumulation) is formed at the back interface for negative VGb, the threshold voltage of devices is increased. For strong inversion condition (VGf > 1.8 V) at the front interface, the gate tunneling current (IGf) begins to aggregate excess holes into the floating body as illustrated in Figure 2.26c. The potential of the back interface increases gradually and influences the front-surface potential via the coupling effect. Once the excess holes prevail into the floating body, the device shows additional current conduction. Indeed, the front-channel threshold voltage is lowered which is leading to a sudden increase of the drain current as demonstrated in Figure 2.27.
This positive feedback mechanism in a floating body device is deemed to enhance the device performance (high transconductance and boosting current) or to be detrimental as a parasitic effect (non-linearity).
Parasitic Bipolar Transistor Effect
In general, the MOSFET structure encompasses a lateral NPN bipolar junction transistor (BJT) inherently, the activation on which relies on the forward biasing of the source-body (i.e., emitter-base) junction. The PBT effect was discussed by Sun et al., regarding the latch-up breakdown in a typical silicon device . In addition, a study by Chen et al  proved that band-to-band tunneling (BTBT) can be amplified by the PBT in short channel SOI devices. Since then, the parasitic bipolar transistor (PBT) has been systematically investigated in partially-depleted SOI MOSFETs and reported by Reichert et al . Particularly, Liu et al. have scrutinized the parasitic bipolar effect in ultrathin FDSOI MOSFETs in terms of holes generated by BTBT . As long as the PBT effect appears in SOI MOSFETs, it has detrimental consequences on the linearity of I-V curve.
In this section, we focus on the parasitic bipolar amplification in ultrathin FDSOI MOSFETs. Based on experiments, the bipolar amplification will be clarified by changing drain voltages and back-gate conditions: accumulation, depletion, and inversion. Likewise, the ultrathin FDSOI MOSFETs without the body contact have also put to activate the innate bipolar device owing to the accumulation of positive charges generated by impact ionization or BTBT. The parasitic bipolar transistor is noticeably effective in short devices as base narrowing of BJT. In an OFF state (VGf < 0), the MOS channel underneath the gate is unformed and the bipolar transistor current becomes more dominant.
Table of contents :
1.1 General Introduction
1.2 Silicon-on-Insulator (SOI) Technology
1.2.1 Scaling Limit of Bulk Silicon MOSFETs
1.2.2 State-of-the-art of SOI Technology
1.2.3 SOI Wafer Fabrication: Smart-CutTM Process
1.3 Ultimate Scalability and Flexibility of SOI Devices
1.3.1 Planar Partially Depleted and Fully-Depleted SOI Devices
1.3.2 Multi-Gate FDSOI Devices
1.3.3 Ultrathin Body and BOX (UTBB) MOSFETs
184.108.40.206 Inter-Gate Coupling Effect: Typical Coupling Mechanism
220.127.116.11 Super-Coupling Effect
18.104.22.168 Short Channel Effects in FDSOI
1.3.4 Compound Semiconductor on Insulator Devices
Chapter 2: Floating Body Effects in Ultrathin FDSOI MOSFETs
2.2 Kink Effect in Ultrathin Fully-Depleted SOI MOSFETs
2.2.1 Experimental Details
2.2.2 DC Measurement
2.2.3 Pulsed-Mode Measurement
2.2.4 TCAD Device Simulation
2.3 Gate-Induced FBE (GIFBE) in Ultrathin MOSFETs
2.3.1 Experimental Details
2.3.2 Current and Transconductance Characteristics
2.4 Parasitic Bipolar Transistor (PBT) Effect
2.4.1 Experimental Details
2.4.2 Transfer Characteristics
2.5 Sharp-Switching and Hysteresis Characteristics
2.5.1 Steady-State Characteristics
2.6 Transient and History Effect: Meta-Stable-Dip (MSD) Effect
2.6.1 Generic MSD Feature and New Memory Effect
2.6.2 Transient Current Evaluation
Chapter 3: Dynamic Body Potential Variation in Ultrathin FDSOI MOSFETs
3.2 Body Potential Measurement in Non-Equilibrium
3.2.1 Experimental Details
3.2.2 DC Characteristics of Body Contacted n-MOSFET
3.2.3 Correlation with FBEs
3.3 Gate Coupling Characterization in Ultra-thin Film Revisited by Body Potential Measurements
3.3.2 Measurement Setup
3.3.4 TCAD Device Simulation
3.3.5 New Approach for Extracting VT in Ultrathin FDSOI MOSFET
Chapter 4: Investigation of Advanced SOI applications
4.2 Back-Gated InGaAs-on-Insulator Lateral N+NN+ MOSFET
4.2.2 Device Fabrication
4.2.3 Measurement Setup: Pseudo Ψ-MOSFET
4.2.4 Current and Transconductance Characteristics
4.2.5 Mobility Evaluation
4.3 Transducers using Z2-FET
4.3.2 Z2-FET Device Operation
4.3.3 Magnetic Sensor
22.214.171.124 Measurement Setup
126.96.36.199 DC Characteristic under Magnetic Field
4.3.4 Optical Sensor
188.8.131.52 Measurement Setup
184.108.40.206 DC Characteristic
5. General Conclusion
6. Contributions and Publications
7. Résumé de la Thès