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Enhanced homojunction model
The homojunction is formed due to the implantation of heavily doped region (i.e, P+ or N+) over low doped material of the same type, such as junctions between P and P+ regions and N and N+ regions. Such junctions can be considered as a connection of two different resistances. The difference in the values of these resistances is extremely large, that can be considered as a resistance discontinuity and the voltage drop abruptly changes. These junctions can be modeled using the same technique used for modeling the PN junction. The total current of a PP+ or NN+ junction can be assumed to be constant. However, for the minority carriers there is an abrupt change in the excess minority carriers concentration.
To illustrate this phenomenon, assume a NN+ junction with a doping concentration of Nd,1 >> Nd,2. At non-equilibrium conditions, the mass action law imposes that the product between minority and majority carriers concentration is the same and it is dependent on the quasi-Fermi levels splitting. Applying the quasi-neutrality condition and low injection case, a relation between the excess minority carriers on both sides can be obtained as in equation 3.40 [Stefanucci14b]. n1p1 = n2p2 (Nd,1 + δp1)(po + δp1) = (Nd,2 + δp2)(po + δp2).
Conventional and enhanced substrate modeling
We are going to illustrate the difference in the extracted netlist using the conventional and the enhanced models.
Conventional substrate extraction
After finishing the layout of the design, parasitic components should be extracted. These parasitic components can be divided into two main categories:
1. Metal interconnects: The parasitic capacitances and resistances for the metal interconnects are extracted.
2. Substrate extraction: The substrate parasitic components are extracted.
The commercial extraction tools that are commonly used for the parasitic extraction are Star RCXTR provided by Synopsys , QuantusTM QRC provided by Cadence R , and Calibre xRC provided by Mentor Graphics R . These tools are used for the analysis of the parasitic noise coupling through the substrate based on modeling the substrate as RC network. The tool providers focus on improving the accuracy and reducing the simulation time. These coupling effects are critical for Mixed-Signal ASICs [Donnay03] and low voltage RF applications [Bronckers09]. However, the lateral parasitic coupling is not considered in the distributed RC model.
Assume a cross-section in HV-CMOS technology as shown in Figure 3.10. The figure shows isolated DNMOS and DPMOS transistors. An isolating guard ring is inserted in between to reduce the coupling between the two transistors and other wells. The solid line components represent the parasitic components that are included in the compact model of the transistors. The dashed line components represent a simple version of extracted netlist by the current commercial tools. On the one hand, we can observe that the vertical parasitic PNP transistor is modeled. On the other hand, the lateral NPN transistors between the three deep N-wells (i.e, DPMOS, DNMOS, and guard rings) are not modeled. The main impediment to model such parasitic components is its dependence on the layout and the circuit operation. For example, if the drain of the DNMOS goes below ground and the guard ring and the N-well of the DPMOS are connected to a high voltage, the resulting structure is a double collector BJT. This simple example can be extended to multi-collector parasitic components.
In high voltage applications, this lateral parasitic components can severely degrade the performance of low voltage circuits or even cause destructive failures due to latch-up. The extraction of these components relies on the hand extraction developed by the designer and some qualitative design rules [Hastings06].
Enhanced substrate extraction
Since the enhanced components, previously presented, model the propagation of minority carriers, the lateral NPN can be seamlessly modeled. The substrate components could be resistance, diode, and homojunctions. The parasitic capacitance is inherently included in the enhanced diode model. The enhanced diode model compromises the diffusion capacitance model in case of forward biasing in addition to modeling the junction capacitance. Therefore, the lateral NPN transistor can be viewed as back-to-back diodes in the substrate network and the multi-collector device can be composed simply based on the extracted components. As depicted in Figure 3.11, the substrate is modeled as a network of enhanced resistances and diodes. The homojunction components are not shown in this figure for simplicity. Two back-to-back connected enhanced diodes have the same behavior as the lateral NPN transistor. The number of the parasitic components depends on the meshing of the substrate.
AUTOMICS: substrate parasitic extraction tool
Minority carriers propagation modeling in the substrate is the stronghold of the proposed modeling scheme, especially for high voltage and high temperature applications. As most of current tools are not considering the minority carriers propagation, the presence of a tool able to model the substrate including the minority carriers propagation would be helpful in the design. A CAD tool developed in LIP6 is able to extract the parasitic substrate components automatically from the layout of a design. This tool is referred as AUTOMICS tool. The extraction procedure has two basic steps:
A. Geometrical features extraction using AUTOMICS tool.
B. Technological parameters calibration.
AUTOMICS tool geometrical features extraction
The main feature of the AUTOMICS tool is to extract the geometrical features of the parasitic components in the layout. The inputs and outputs of the tool is depicted in Figure 3.12. The main flow of the tool can be divided into three main steps [Zou15]:
1. pre-processing stage.
2. extraction stage.
3. post-processing stage.
Proposed design flow for smart power ICs
The proposed design flow is illustrated in Figure 4.2. Since the main substrate noise source under investigation is the lateral NPN transistor, the basic concept depends on the ability to reproduce failures due to this noise in the simulation environment as shown in Figure 4.2(a). If we successfully reproduce the failures then we are able to prevent these failures before the fabrication as in Figure 4.2(b). Consequently, using reliable tool and technology parameters, the number of redesigns due to such failures is reduced and hence the cost and time-to-market are reduced. Besides, all the simulations are done in SPICE-like simulator environment, hence, the simulation time is significantly shorter than TCAD simulations. The proposed design flow has two additional stages in the design flow which are :
1. Failure analysis and reproduction,
2. Substrate parasitic extraction step.
DC-DC buck converter analysis
In this section, the principles used in the switching converter analysis are discussed. Then, the basic open loop equation describing the output voltage as a function of the input voltage is derived. Finally, the control methods used to maintain the output voltage constant is elaborated.
Switching converter analysis principles
In the analysis of DC-DC converters, three principles are used to facilitate the analysis and systematically derive the design equations for the converters [Erickson01]. Small ripples approximations In the DC-DC converters, the voltages and currents contain some ripples due to the switching operation. Generally, the ripples should be minimized. Thus, the ripples of continuous signals can be ignored to simplify the analysis. This approximation can not be applied to the discontinuous signals such as switching node voltage. ripples ≈ 0.
Table of contents :
Contents
List of Figures
List of Tables
List of Abbreviations
List of Symbols
R´esum´e Etendu en Fran¸cais
0.1 Introduction
0.2 M´ethodologie pour la v´erification des circuits int´egr´es de puissance intelligents
0.2.1 Analyse de d´efaillance
0.2.2 Extraction des parasites du substrat
0.3 Convertisseur de tension DC-DC
0.3.1 Fonctionnement du convertisseur DC-DC
0.3.2 Effets du couplage de substrat sur la tension du bandgap .
0.3.3 M´ecanisme d’injection du courant dans le substrat .
Cas de test 1 : on consid`ere les diodes de bulk et de substrat
Cas de test 2 : on consid`ere seulement la diode de substrat
0.4 Etude de cas industriel : Autochip 1
0.4.1 M´ethode classique d’identification du probl`eme
0.4.2 Proposition d’identification du probl`eme
0.5 Conclusion
1 Introduction
1.1 Motivation
1.2 Contribution
1.3 Thesis outline
2 Substrate modeling state of the Art
2.1 Introduction
2.2 State of the art in substrate modeling
2.2.1 Substrate modeling in analog-mixed circuits
2.2.2 Substrate modeling in high voltage circuits
2.3 Conclusion
3 AUTOMICS: Pragmatic substrate parasitic extraction framework
3.1 Conventional Substrate modeling components
3.1.1 Resistance in conventional substrate modeling
3.1.2 PN junction in conventional substrate modeling
3.1.3 Capacitance in conventional substrate modeling
3.2 Enhanced substrate modeling components
3.2.1 Enhanced resistance model Minority carriers diffusion equivalent circuit
3.2.2 Enhanced PN junction model
3.2.3 Enhanced homojunction model
3.3 Conventional and enhanced substrate modeling
3.3.1 Conventional substrate extraction
3.3.2 Enhanced substrate extraction
3.4 AUTOMICS: substrate parasitic extraction tool
3.4.1 AUTOMICS tool geometrical features extraction
AUTOMICS tool pre-processing stage
AUTOMICS tool extraction stage
AUTOMICS tool post-processing stage
3.4.2 Model parameters calibration
3.5 Conclusion
4 Proposed design flow for smart power ICs
4.1 Conventional design flow for smart power ICs
4.2 Proposed design flow for smart power ICs
4.2.1 Failure analysis and reproduction
4.2.2 Substrate parasitic extraction step
4.3 AUTOCHIP 1: Industrial case study
4.3.1 Conventional problem identification
4.3.2 Proposed failure analysis
AUTOMICS parasitic extraction of AUTOCHIP1
Substrate network simulation
4.3.3 Proposed solutions for latch-up problems
4.4 Conclusion
5 DC-DC buck converter system level design
5.1 Power supplies in automotive industry
5.1.1 Power supply classification
5.2 DC-DC buck converter analysis
5.2.1 Switching converter analysis principles
Small ripples approximations
Inductor volt-second balance
Capacitor charge balance
5.2.2 Derivation of large-signal equations
Output voltage
Inductor current ripples
Output voltage ripples
Power Losses and efficiency of buck converter for CCM
Systematic design procedure
5.2.3 Derivation of small-signal equations
5.3 DC-DC buck converter system level design
5.3.1 Voltage mode control (VMC)
Voltage mode control closed loop
Systematic design of VMC closed loop
5.3.2 Current programmed mode (CPM) control
Control current to duty cycle transfer function
Closed loop system for CPM control
5.4 Proposed analog-mixed PI controller in low switching frequency
applications
5.5 Conclusion
6 DC-DC buck converter circuit and measurements
6.1 DC-DC buck converter circuit operation
6.2 DC-DC buck converter circuit building blocks
6.2.1 Switches and drivers circuits
Switches
Switches gate drivers
6.2.2 Pulse level shifter circuit
6.2.3 HV comparator circuit
6.2.4 Bandgap circuit
6.2.5 Oscillator circuit
6.2.6 Sawtooth generator circuit
6.2.7 Proportional Amplifier
6.2.8 Voltage-to-current converter and current limiter
6.2.9 Deadtime generator circuit
6.3 Circuit simulation results
6.4 Chip floorplanning
6.5 Chip measurements
6.5.1 Low voltage measurements
6.5.2 High voltage measurements
6.6 Effects of the substrate coupling on the bandgap voltage .
6.6.1 Bandgap circuit
6.6.2 Substrate injection current mechanism
Test case 1: the body and substrate diodes are considered
Test case 2: the substrate diode is only considered
6.7 Conclusion
7 Summary and Future Work
7.1 Thesis summary
7.2 Future work
Publications
Appendix A. DC-DC buck converter Power losses
References
