Gallium nitride nanowires on graphene

Get Complete Project Material File(s) Now! »

Means of obtaining thin polycrystalline-Si layers

As seen in the previous section, Si is one of the main hetero-epitaxial substrates being actively explored for growth of GaN NWs. GaN-on-Si has been emerging so fast in the past decade that it could be considered as a matured technology. In most of the cases, bulk crystalline Si wafers with a (111) orientation are used as substrates by overcoming the lattice mismatch and the thermal expansion coefficient mismatch by using intellectual property (IP)-protected buffer layers1. This is less interesting when we take into account the large material loss (because of the bulk substrate) and the inaptness to the future scope of producing flexible devices. It is therefore important to use a means to obtain thin Si layer which could act as a thin-flexible-supports for high quality material growth.
One approach is to grow Si thin film epitaxially on a crystalline Si wafer with a sacrificial layer and detach them to produce free standing thin substrates2. Though it enables to produce large area monocrystalline Si templates, the process is limited by the size of the Si wafers (not individually scalable) and introduces significant cost and complex processing steps3. Another common way to obtain thin Si layer is by means of plasma enhanced chemical vapour deposition (PECVD). However, this method produces amorphous Si layers or polycrystalline Si layers with the grain size in the orders of nm4. Though this could be sufficient for NW based devices due to the small footprint of NWs, it is impossible to scale to micro-structures (micro-rods or micro-disks having footprint in the orders of μm) as it might induce defects from the grain boundaries of Si. With CVD at high temperatures (>700 oC), it is possible to grow polycrystalline Si directly on any foreign substrate4. The size of the grains is controlled in the nucleation phase and are typically in the range of 2-20 μm. The layers obtained often present a [110] fiber texture5 which is due to the fact that [110] oriented grains grow faster than others. Thus the texture quality is much stronger as the thickness of the layer increases. However, it is not an indication of the layer quality as twinning defects are commonly observed in such layers with high fiber texture quality4. Another important method to obtain crystalline Si films is by deposition of amorphous Si (a-Si), and a subsequent annealing step to crystallise Si. This method involving a simple annealing step of a-Si for many hours, is referred by the term “Solid Phase Crystallisation” (SPC)6,7. Deposition of a-Si can be obtained in many ways like CVD7 and sputtering8. The layer is then annealed for several tens of hours at a temperature between 550 oC and 700 oC9. By this method the higher the temperature, the faster the crystallisation, but also smaller the grain size6. This method of crystallisation is generally used for layers having a thickness of 1 μm and the grains have an aspect ratio close to unity and feature a [111] fiber texture. But the main drawback with this method is the long annealing duration to get good quality fiber-texture layer, calling for a compromise between layer quality and the duration of the process6,9.

Growth of Si nanowires on AIC-Si substrate

Kendrick et al.28, have grown Si NWs by VLS mechanism on fused quartz supports using AIC-Si as the substrate. Samples were prepared with AIC-Si annealed at 500 °C for more than 24 hours. Si NWs were grown using CVD at around 1000 °C with Au as the catalyst. They have investigated the AIC-Si layers deposited using sputtering and e-beam evaporation and found that e-beam evaporated AIC-Si stack produces better [111] fiber texture quality. TEM results show that the Si NWs grew epitaxially with the AIC-Si surface. And also that Si NWs grew on AIC-Si layer in island fashion only on places where [111] fiber textured pc-Si layer was formed. This indeed again stresses the importance of fiber-texture quality on the alignment of NWs and on the usage of AIC-Si as substrates for epitaxy.

High density GaAs NWs on AIC-Si

Recently D. Ren et al.29, have shown that it is possible to obtain high density GaAs NWs on the AIC-Si substrates. E-beam deposited AIC –Si layers were annealed at 500 °C to have a [111] fiber-texture and have been used for growth of GaAs NWs by VLS mechanism by molecular beam epitaxy at ~625 °C. GaAs NWs were grown by modifying the surface oxide condition after the pc-Si formation. Based on the contact angle formed by the Ga catalyst droplet on the surface oxide present on pc-Si, the growth of GaAs could vary from almost no NWs to NW+parasitic growth to highly dense NWs. Additionally, they have also shown that by adding Sb during the growth of NWs, the yield of vertical NWs can be improved. Finally by photoluminescence measurements, it has been shown that GaAs NWs grown on AIC-Si layers are of high quality, similar to the NWs grown on monocrystalline Si(111) substrates validating the previous observations for GaAs NWs24.

Thermodynamics of AIC-Si formation

In order to optimise the layer quality of the final polycrystalline silicon (pc-Si), it is necessary to understand in detail the mechanism of AIC-Si formation. In this section we will see the detailed understanding of the AIC-Si formation found in literature. These studies form the basis from where we started our research in optimising the AIC-Si layer.
The more detailed understanding of the AIC mechanism involves the study of a-Si/Al interface. By thermodynamic considerations, amorphous materials strive to crystallise because the Gibbs free energy of crystalline state is lower than the amorphous state9. But due to the strong covalent bonding (3.30 eV for Si-Si) present between the atoms, exists a high activation energy for the conversion of a-Si to c-Si. Usually the overcoming of this barrier is achieved by thermal activation and requires a temperature of about 700 oC for Si. When an amorphous semiconductor is in contact with a metal, this thermal activation temperature decreases indicating the activation barrier is reduced somehow. Experiments by Hiraki et al. showed that the strong covalent bond in semiconductors can be weakened at the interface by the presence of a metallic layer30,31,9. The a-Si atoms present at the Al/a-Si interface undergo covalent bond weakening by Coulomb screening effect, and this promotes an enhanced mobility of the Si atoms 32,9.

Essence of intermediate oxide layer

Intermediate oxide layer plays a significant role in the fiber texture quality of pc-Si layers39,40. Kurosawa et al.39, have reported that lack of an intermediate oxide (IMO) layer results in randomly oriented pc-Si layer whereas with sufficient thickness of intermediate oxide, Si(111) fiber texture was produced. The intermediate oxide layer is explained to act as an inter-diffusion barrier for a-Si at low annealing temperatures. Depending on the thickness of silica, the group demonstrated Si(100) and Si(111) fiber textured pc-Si layers. In their experiments, the oxide layer was prepared by exposing the sample to air for different duration of time. Thin layer of IMO (5 minutes exposure to air) at the interface of a thick a-Si/Al (100 nm) stack produces Si(100) oriented layer while thicker layer of IMO (24 hours exposure to air) for the same stack produces Si(111) oriented pc-Si. Further results reported by Okada et al.40 showed that there is a presence of an optimal thickness IMO layer for specific thicknesses of AI-Si stack above which the fiber-texture is again affected. In their case, for a a- Si/Al stack of 100 nm each, 10 nm is the optimal thickness of IMO to produce a factor close-to-unity of 111 fibertextured c-Si layers.
Apart from controlling the orientation of the fiber-texture, IMO thickness also plays a role in controlling the growth rate of c-Si40. It shows that IMO acts a permeable layer in diffusion of a-Si into the Al grain boundaries. In fact, it has been shown that IMO plays a crucial role in controlling the dissolution of a-Si in Al at the a-Si/Al interface at high annealing temperatures (close to the eutectic temperature)9.

READ  Consistency of the MLE for the Class of Fully Dominated Markov Chains 

3.2.2 Preparation and optimisation of thin Si layers

In this section we will explain in detail about the layer preparation process, right from deposition to crystallisation of Si and removal Al to have the final pc-Si layer ready for growth NWs on them. In our case we have used a growth support consisting of 25 nm SiO2 layer thermally grown on Si (100) quarters to replicate the properties of a glass or amorphous support. Deposition of the layers

There are different means of depositing thin film of amorphous semiconductors. Chemical vapour
deposition (CVD) techniques like low-pressure CVD (LPCVD), PECVD, MOCVD, APCVD can be used to prepare amorphous semiconductors at low temperatures. Other techniques include sputtering (DC sputtering, DC magnetron sputtering, RF sputtering), evaporation (thermal evaporation, ebeam evaporation) and reactive PVD. Though PECVD is the most common method in industry, in our experiments, we have used DC magnetron sputtering for the synthesis of thin layers of a-Si and Al, mainly for the relative low cost and high uniformity of the deposited layers. As seen before, a typical AIC-Si stack layer consists of layer of Al, thin oxide layer and a layer of a-Si. In most cases, the intermediate oxide layer isprepared by exposing the Al layer to ambient conditions overnight (few hours) to form native AlOx and then depositing of a-Si layer on top of it34,35. This is not only time consuming but also produces a completely uncontrolled interfacial layer of SiO2. In our case we used an in-situ oxide preparation method to produce a controlled layer of SiO2 intermediate layer.

Table of contents :

Table of contents
General Introduction
Organization of this thesis
Chapter 1: Necessity for a novel substrate for gallium nitride nanowires
1.1 Gallium Nitride: An introduction
1.1.1 A brief history of GaN crystal growth
1.1.2 Substrates for epitaxial growth of GaN
1.2 Introduction to Nanowires
1.2.1 Advantages of nanowires
1.2.2 NW growth by PAMBE
1.3 Novel substrates for GaN NWs
1.3.1 Motivation
1.3.2 State of the art: NW growth on non-conventional substrates
1.3.3 Objective of this project
Chapter 2: Conventional gallium nitride nanowires growth on Si(111) bulk substrate
2.1 Introduction and state-of-the-art
2.1.1 Brief introduction
2.1.2 State-of-the-art
2.2 Standard growth conditions and results
2.2.1 Substrate preparation
2.2.2 Substrate temperature calibration
2.2.3 Flux calibration
2.2.4 Aluminium Nitride pre-deposition
2.2.5 GaN NW growth
2.2.6 Characterisation of GaN NWs Morphology of the NWs Pole-figure measurements Polarity of the NWs Photoluminescence measurements
2.3 Summary
Chapter 3: AIC-Si as a substrate for gallium nitride nanowire growth
3.1 Introduction and objective
3.1.1 Means of obtaining thin polycrystalline-Si layers
3.1.2 Aluminium induced crystallization of Si (AIC-Si)
3.1.3 Potential substrate for NW growth Fiber texture Proof of concept for GaAs NWs
3.1.4 State of the art: AIC layers as substrate for NW epitaxy Growth of Ge nanowires on AIC-Ge substrates Growth of Si nanowires on AIC-Si substrate High density GaAs NWs on AIC-Si
3.1.5 Objective of this work
3.2 Synthesis of AIC-Si
3.2.1 Thermodynamics of AIC-Si formation Al/Si ratio Annealing process Essence of intermediate oxide layer
3.2.2 Preparation and optimisation of thin Si layers Experimental section Deposition of the layers Crystallisation and surface treatment Optimisation of the layer Possible minimum thickness for continuous c-Si layer Surface roughness and fiber-texture quality
3.3 GaN nanowires on AIC-Si
3.3.1 Growth of GaN nanowires on continuous AIC-Si layers
3.3.2 Characterisation of the NWs Verticality of NWs Polarity of NWs
3.3.3 Surface deformation
3.4 Growth on patterned AIC-Si
3.4.1 Preliminary results for selective growth
3.4.2 Fabrication of AIC-Si nano-islands by lithography
3.4.2 Vertical GaN NWs on AIC-Si nano-islands
3.5 Conclusion and future scope
Chapter 4: Gallium nitride nanowires on silica
4.1 Introduction and objectives
4.1.1 Amorphous Substrates
4.1.2 Objective
4.2 State of the art: Silica substrate
4.3 GaN nanowires on silica
4.3.1 Thermal and fused silica substrates preparation
4.3.2 Growth of GaN NWs
4.3.3 Growth evolution
4.4 Characterisation
4.4.1 Structural quality Verticality TEM analysis Polarity Bushes
4.4.2 Optical quality
Conclusion and future scope
Chapter 5: Gallium nitride nanowires on graphene
5.1 Introduction and objectives
5.1.1 A brief introduction to graphene
5.1.2 Van der Waals epitaxy
5.1.3 State of the art: Graphitic substrates
5.1.4 Objective
5.2 GaN nanowires on graphene
5.2.1 Different type of graphene layers Preparation of graphene patch samples Preparation of graphene flake samples
5.2.2 Growth of GaN NWs On graphene monolayer patch On graphene flakes Silica intermediate layer
5.3 Characterisation
5.3.1 XRD and Pole-figure results
5.3.3 TEM results
5.3.4 Photoluminescence results
5.4 Epitaxial growth of GaN on graphene
5.4.1 Lattice relationship with graphene SEM observation SAED patterns
5.4.2 Epitaxial growth configuration
5.4.3 Difference in NW nucleation with respect to different number of MLs of graphene*
5.5 Proof of concept for selective area growth of NWs on graphene
5.5.1 Patterning process of graphene
5.5.2 Growth on micro- and nano- patches of graphene ML
5.6 Conclusion and future scope
A.1 Crystal properties of GaN
A.2 Defects and dislocations in GaN
A.3 Plasma assisted molecular beam epitaxy (PAMBE)
A.4 Reflective high energy electron diffraction (RHEED)
A.5 X-ray diffraction (XRD)
A.6 Photoluminescence


Related Posts