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3D Packaging

Over the last decade, wire-bonding has been the dominant interconnection technique for power devices due to its maturity. However, in the area of high-power or hightemperature applications, there are a lot of limitations concerning high stray inductances, mechanical damage or mutual coupling effects [51]. In addition, the two-dimensional packaging structure has limited heat-dissipation capability. In order to improve electrical and thermal characteristics and to reduce package size, researchers and manufacturers have focused on non-wirebond three-dimensional (3D) packaging solutions.

Metal post interconnection technology

The metal post interconnection technology is based on copper posts which are soldered on to the bonding pads of the processed devices. One of this 3D assembly is called the metal post-interconnected parallel-plate structure (MPIPPS).
Elimination of the wire bonds significantly reduces the inductance generated by the interconnections. A study shows that a copper post generates only 1.27 nH [51] [52]. Additionally, the copper post can be machined to maximize the contact area with the bondable surface of the die, further reducing the overall inductance. Another important objective of the MPIPPS design is to improve the heat dissipation capability of the package. This technology allows a double side cooling, and some of the heat dissipated by the devices can be removed through the copper posts [53]. Thermal modeling of the MPIPPS module and a comparable wire-bond module showed that the maximum junction temperature on the IGBT chips in the MPIPPS module can be lowered than the wire-bonded module by 17 °C [51].

Solder bump interconnection technology

The solder bumping interconnection is based on the deposition of flip-chip solder bump on the power device [54]. The solder bump can be made of lead-free Pn/Sn, Sn/Ag or Au (Figure 1.20). This technology is used in the micro-electronic domain to decrease the assembly size and improve its electrical and thermal performance. Besides, several semiconductor manufacturers develop their power components with this technology in order to reduce the parasitic inductance and voltage drop for very low voltage components (Fig.1.6). In an effort to further optimize solder bump connections, a novel triple-stacked solderbump geometry was developed [55] for enhanced reliability of the joints. This geometry involves additional solder deposition and reflow steps and the use of several alloy types with different melting points to form the stacked structure whereas common flip-chip interconnections make use of a single reflow process to produce a solder bump. The construction process seems more complex, but it provides the ability to control the joint height and shape while maintaining compatibility with surface mount technology. In a production environment, it may be possible to do away with the extra alloys and reduce the number of reflows into a single step. Different solder alloys with different melting temperatures are needed to preserve joints formed in a previous reflow. The stacked joint can either have an hourglass or barrel shape, shown in Figure 1.21.

Dimple array interconnection technology

The dimple-array interconnect (DAI) (shown in Figure 1.22) is a 3D packaging technique, where the electrical interconnection is established by the formation of solder bumps between device electrodes and the preformed array of dimples on a flexible metal sheet (thickness between 50 μm and 400 μm) [57, 58]. The result is a low-profile planar interconnection that is suitable for multilayer integration with other components. The soldered dimples form interconnecting joints that take the natural shape of an hourglass. Which enhances the reliability of the joint compared to a barrel-shaped geometry. With the exception of fabricating the dimpled copper sheet, the DAI process follows the typical solder joint fabrication process. Copper is the preferred material for the dimpled metal sheet due to a favorable combination of low cost, ease of formability, and high electrical and thermal conductivity.

Direct solder interconnection technology

The direct solder interconnection technology consists in soldering the top and the bottom side of the chip on a ceramic substrate [51]. Figure 1.23 shows a 3D assembly where the source and gate side of a MOSFET were attached simultaneously with the drain side using large area lead-free solder paste (Sn- 3.5Ag) [51]. This technology is easier to implement compared to other soldering-based interconnection. Besides, because the direct solder is thin (about 100μm) and has the same area as the die, this type of interconnection has a lower thermal and electric resistance [51]. Furthermore, this approach enables dualside cooling. Figure 1.24 shows a comparison of the temperature distribution in the solder bump and direct solder packages obtained by thermal analysis where a heat dissipation of 8 W was used for the power MOSFET, and an equivalent heat-transfer coefficient of 1000 W/m K from both surfaces of the DBC substrates was assumed [61].

Thermal and electrical issues of package

As the EPC GaN transistors are lateral devices, all terminals (solder bumps) are located on the same side of the die. This is efficient from an electrical point of view, with very short distances between the active area of the GaN transistor and the other components of the converter. From a thermal point of view, however, this is not so efficient: the bumps have limited thermal conductivity, and cover only a fraction of the die surface area. Therefore, before realizing the final module, it is worth firstly comparing the thermal performance of GaN transistors cooled either through their bumps (topside cooling) or through their silicon substrate (backside cooling) to choose the better solution.
Another important element to improve the thermal performance is to choose an appropriate substrate. In fact, to enable the high switching speed available from the eGaN FETs, the PCB substrate is usually be used for its low inductance interconnect (in the case of multilayer PCBs). However, this substrate is usually dedicated to small power application and it has poor thermal conductivity. A widely used substrate in power electronics domain is the ceramic substrates (especially DBC, for Direct Bonded Copper), which are preferred for medium to large power packages (from kW to MW). In particular, alumina (Al2O3) is commonly used and offers thermal conductivities of 24 to 33 W/mK. The dielectric strength of ceramic is lower (from 10 to 15 kV/mm) than that of typical epoxy-based FR4 PCBs (54kV/mm). Therefore, PCBs may be thinner than alumina substrates for the same insulation rating. From a thermal point-of-view, however, the possible difference in thickness is not sufficient to make up for the difference in thermal conductivity. Thermalvias are often used to reduce the thermal resistance of PCBs, but they are electrically conducting.
Three functioning prototype designs are fabricated to compare the cooling solutions for GaN transistors. Their cross-section structures are shown in Figure 2.6. In the first configuration (prototype I), GaN transistors were flip-chip-mounted on a DBC substrate  with an alumina layer of 635 μm. A special etching technique was used to achieve the high resolution (200 μm pitch) required to mount the transistors. In the second configuration (prototype II), the backside of the transistors was attached to the DBC substrate. This required grinding down the silicon substrate of the transistors, to reduce their thickness and to remove the marking. A Ti/Ag layer was deposited on the silicon substrate, and the dies were attached to the DBC substrate using silver sintering. A flex substrate is used on the topside for the electrical interconnects. The third configuration (prototype III) is the classical flip-chip mounting on PCB (albeit on a much thinner PCB than usual, to improve its thermal performance), used as a basis for comparison. The three prototypes are shown in Figure 2.7.

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Table of contents :

1.1 Introduction
1.2 Power Converters
1.2.1 Active Components GaN power devices SiC power devices
1.2.2 Switching cell Parasitic elements and their issues
1.2.3 Multicell power converter
1.3 Power Packaging
1.3.1 2D Packaging Structure Limiting points
1.3.2 3D Packaging Metal post interconnection technology Solder bump interconnection technology Dimple array interconnection technology Direct solder interconnection technology Embedded power technology Press Pack technology Spring contact technology PCB technology
1.3.3 Conclusion
1.4 Fabrication Process
1.4.1 Solder
1.4.2 Sintering
1.4.3 PCB technology
1.5 Conclusion
2.1 Introduction
2.2 Proposed structures
2.2.1 Presentation of the GaN components
2.2.2 Thermal and electrical issues of package
2.3 Fabrication process
2.3.1 DBC preparation Substrate cleaning Photolithography
2.3.2 Reflow Soldering
2.3.3 Prototype I: Flip-chip with DBC
2.3.4 Prototype II: “Flip flip” chip on DBC
2.3.5 Prototype III: Flip-chip on PCB
2.3.6 Conclusion
2.4 Thermal analysis
2.4.1 Thermal conduction
2.4.2 Thermal convection
2.4.3 Thermal Radiation
2.4.4 FEM analysis
2.4.5 Thermal simulation of GaN prototypes
2.4.6 Experimental characterizations
2.4.7 Conclusion
2.5 Electromagnetic and electric study
2.5.1 Half-bridge demonstrator
2.5.2 Electromagnetic analysis Wire bonding prototype GaN Prototypes Analytical approach for partial inductance
2.5.3 Electric analysis Electrical Simulation Experimental characteristics
2.6 Conclusion
3.1 Introduction
3.2 Proposed structures for the analysis of the contact
3.3 Fabrication process
3.3.1 PCB materials used in fabrication Isola PCL370HR and Arlon 55NT Release film and press-pads
3.3.2 Chemical Ag deposition
3.3.3 Chip preparation
3.3.4 Ag Sintering
3.3.5 Detailed description of the process PCB embedding Etching
3.3.6 Laser ablation
3.3.7 Metallization
3.4 Static characterization of the embedded diode
3.5 Analysis of electric contact
3.5.1 Modelling
3.5.2 Experimental measurement
3.5.3 Conclusion
3.6 Half bridge prototype
3.6.1 Layout adaption for component surface IGBT Diode
3.6.2 Process flow
3.6.3 Manufacturing data generation
3.6.4 Design Tolerance
3.6.5 FEM simulation
3.6.6 Experimental characterization
3.6.7 Improvement
3.7 Conclusion


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