Trends of micro/nanoelectronics
The invention of the transistor in 1948 is arguably the major technological break-through of the 20th century. The transistors are the building blocks of today’s mi-croprocessors and computers that are everywhere around us. Nowadays, billions of transistors are integrated on a microchip of only a square centimeter. Since the Nobel prize attributed to Shockley, Brattain and Bardeen in the 1956, and the inven-tion of integrated circuits in the same decade, considerable efforts have been put to keep miniaturizing the metal oxide semiconductor field effect transistors (MOS-FETs). A conventional MOSFET structure with descriptions of its working prin-ciple are shown in Fig.1.1. From one technology node to the other, MOSFETs are conceived to be smaller (following Moore’s law), faster and less power consuming. Thirty years of aggressive scaling have pushed the device dimensions close to the atomic range. The downscaling of MOSFETs has slowed down since the 65 nm node was reached. Issues related to the nanoscale dimensions of the devices started aris-ing.
When the channel length is decreased below 1 m, additional problems appear and are commonly called short-channel effects (SCEs). The SCEs for the MOSFETs are important when the channel length becomes comparable to the width of the deple-tion region. When the gate length is scaled down, the gate starts to lose the electro-static control over the channel, on the other hand the source-drain bias (VDS) gains a larger influence on the barrier. Such an effect is named drain-induced barrier low-ering (DIBL). This loss of electrostatic integrity leads to a continue increase of the current and decrease of the off-state potential.
Moreover, the electron mobility is reduced due to collisions with the semiconduc-tor/oxide interface. This surface scattering effect is enhanced by the increase of electric field in the confined regions, which pushes the electrons toward the surface of the device. The reduction of electron mobility is also caused by the necessity of using high doping levels in such scaled MOSFET. Finally, the average velocity of carriers does no longer linearly depend on the electric field in such small devices, which is called the velocity saturation.
FIGURE 1.1: Schematic cross-section of a N-channel MOSFET: (a) 0 V gate bias, (b) positive gate bias that charges the gate. The P-type substrate below the gate takes on a negative charge. An inversion region with an excess of electrons forms below the gate oxide. This region connects the source and drain N-type regions, forming a continuous N-region from source to drain.
The drawbacks of traditional bulk planar transistors have promoted the search for new architectures alternative to MOSFETs. The International Technology Roadmap for Semiconductors (ITRS) , which evaluates the technology requirements for the next-generation semiconductor device technology, predicts that additional new ma-terials and transistor geometries will be needed to successfully address the formidable challenges of transistor scaling in the next 15 years. In Table 1.1, some main figures of merit extracted from the ITRS for the short- (2018) and long-term (2026) technolo-gies, both for high-performance and low-power applications. Since the late ’90s, it has been suggested to replace single-gate transistors by multi-gate structures in or-der to enhance the electrostatic control of the gate. Intel has already switched to the TriGate FET, also known as the FinFET, technology since the 22 nm node. Silicon-on-insulator has also been widely used to improve the performances of transistors, especially decreasing leakage currents .
To meet the requirements set by the ITRS for future nodes, scaling down the gate length is critical. The two-dimensional materials (2DMs) provide the ability to con-trol the channel thickness at the atomic level, which will result in improved gate control over the channel and in reduced SCEs. In next Chapter, I will discuss the properties of 2DMs and their numerous possible applications in the electronic de-vices.
Power consumption issues
Power consumption is a fundamental problem for nanoelectronic circuits. To give some examples, all the smartphones need to be recharged everyday; the data cen-ters in the US used 91 billion kilowatt-hours of electricity in 2013.
FIGURE 1.2: (a) Transfer characteristics (drain current ID vs. gate voltage VG) of a MOSFET switch showing an exponential increase in IOFF because of the thermionic limit of the subthreshold swing SS. Here the simultaneous scaling down of the supply voltage VDD and the threshold voltage VT, keeping the same ION by keeping the (VDD-VT) constant. (b) Qualitative comparison of the MOSFET switch (red) with a TFET (green) which has a steep off-on transition and a lower IOFF. At low VG, because of the subthermionic SS, the TFET offers a better performance and power reduction. At high VG, the MOSFET switch becomes a better solution for higher performance thanks to the higher ION.
where is called the activity factor, fc denotes the clock frequency, CL is the load capacitance (mostly gate and wire capacitance, but also drain and some source ca-pacitances), and IOFF is the off-state current. In the formula above, we can identify an operating and a stand-by power that both depend on VDD. Lowering VDD is thus necessary to decrease the consumption. However, a strong VDD reduction signifi-cantly affects the performances of MOSFETs, as illustrated in Fig.1.2(a). Indeed, the problem resides in the speed at which the transistor passes from the off- to the on-states as a function of the gate voltage. In the subthreshold regime of MOSFETs, the thermionic effect entails that at least 60 mV are necessary to increase the current by one order of magnitude at room temperature. In other words, the subthreshold where kB is the Boltzmann constant, T is the temperature taken at 300 K and e is the absolute value of electron charge. If we keep the same on-current ION for the transistor while reducing VDD, then IOFF increases exponentially, see Fig.1.2(a).
A possible way of reducing the voltage supply without performance loss is to in-crease the turn-on steepness, which means decreasing the average SS below the SSmin. Such devices, called steep-slope switches, are expected to effectively enable power scaling. Because of these MOSFET limitations, other device architectures are under active investigation, including the negative-capacitance FET (NC-FET) and the Tunnel FETs (TFETs) .
Tunnel field-effect transistors
In this work, I focus on the TFETs [4–6]. In contrast to MOSFETs, where charges are thermally injected over a potential barrier, the primary injection mechanism is band-to-band tunneling (BTBT), i.e. charge carriers transfer from one energy band into another. This tunneling mechanism was first identified by Zener in 1934 .
A typical TFET is composed of a p-i-n structure with a gated intrinsic region, see Fig.1.3(a). Its working mechanism can be explained as follows. When a low voltage is applied to the gate, electrons tunneling from the valence band of the source to the conduction band of the drain is suppressed due to the gap in the intrinsic region, see Fig.1.3(b). This is the off-state. When the potential applied to the gate brings the conduction band of the intrinsic limit at the same level as the source valence band, electrons can easily tunnel from source to drain, see Fig.1.3(b). This is the on-state. In the ideal case, the transition from the off-state to the on-state is very fast, since the thermal tail of the injected electrons is cut by the top of the valence band in the source and the off-current is exponentially suppressed when the source Fermi level is within the gap of the intrinsic region. This would allow, in principle, very low SS, below SSmin, see Figure 1.2(b).
Here, I briefly summarize the history of TFETs. The gated p-i-n structure was pro-posed in 1978 by Quinn et al. . In 1992, Baba  fabricated TFETs called surface tunnel transistors in group III-V materials. In 1995, Reddick and Amaratunga  reported experiments on silicon surface tunnel transistors. In 2000, Hansch et al.  published experimental results on a reverse-biased vertical silicon TFET fabricated by molecular beam epitaxy. Aydin et al.  fabricated lateral TFETs on silicon-on-insulator in 2004. Recently, TFETs fabricated in various materials (carbon, silicon, SiGe and group III-V materials) have emerged experimentally as the most promising candidates for switches with ultralow standby power and sub-0.5 V supply voltage.
The goals for TFET optimization are to simultaneously achieve the highest possible ION, the lowest average SS over many orders of magnitude of drain current, and the lowest possible IOFF. For TFETs, SS decreases with the gate voltage, therefore they are naturally optimized for low-voltage operation. To achieve a high tunneling cur-rent and a steep slope, the transmission probability of the tunneling barrier should pass from 0 to close to 1 for a small change in gate voltage around the threshold potential. This requires a strong modulation of the channel bands by the gate and a very thin channel barrier.
As mentioned above, there have already been many experimental attempts to build TFET with bulk silicon and III-V group materials. Even though encouraging exper-imental results have been reported for the on-current and SS in Si- and III–V-based TFETs, these devices are very demanding in terms of gate control . Moreover, their transfer characteristics can be seriously degraded by the presence of interface or bulk defects enabling inelastic trap-assisted tunneling in the OFF-state [14, 15].
The 2-D materials (2DMs) may overcome some of the above issues , and have great potential for TFETs, due to their scalability and absence of dangling bonds at interface. They can be stacked to form a new class of tunneling transistors based on an interlayer tunneling occurring in the direction normal to the plane of the 2DMs . In the next Chapter, I will review the properties of various different 2DMs and their applications in the electronic devices.
Quantum transport simulation
The fabrication of novel devices is a long and expensive process. Theoretical in-vestigations are then necessary to guide the semiconductor industry toward more efficient architectures. In this work, simulation tools based on state-of-the-art semi-conductor physics have been developed for studying and designing future TFETs, with emphasis on 2DMs-based TFETs. To properly describe and model the tunnel-ing current flow in TFETs, we need to develop a simulation approach able to take into account quantum phenomena as well as non-ideality effects due to phonon as-sisted tunneling. With appropriate simplifications to overcome the computational difficulties, the Non-Equilibrium Green’s Function (NEGF) formalism provides a suitable framework to simultaneously treat the quantum transport of coherent car-riers and the impact of diffusive phenomena such as electron-phonon interaction.
In the literature, there exists some simulation works on the 2DMs-based TFETs and MOSFETs [18–25]. However the design of the van der Waals TFET (vdW-TFETs) is still largely unexplored , because of the complexity to model the in-terlayer tunneling between the two 2D layers. The effects of electron-phonon scat-tering on the device performance also need better understanding. My thesis work trys to clarify these questions by implementing the NEGF formalism including the electron-phonon self-energy within the self-consistent Born approximation for the vdW-TFETs.
The theoretical elements of this approach will be reviewed and discussed in Chap-ter 3, especially with external perturbations via the so-called self-energy. In Chapter 4 the numerical implementation of the NEGF formalism is provided. These two Chapters build up the heart of all the calculations carried out in the rest of the the-sis. The first application of the developed numerical code is reported and analyzed in Chapter 5, and regards a 2-D TMD-based vertical TFET. In Chapter 6, electron transport in van der Waals TFET (vdW-TFETs) based on MoS2 and WTe2 monolay-ers is studied. In the last years, a special attention has been addressed on the van der Waals tunneling and Esaki diodes [26, 27], and a first device with subthermionic characteristics realized . Then in Chapter 7, an exploratory investigation of the effect of rotational misalignment within stack of 2-D materials will be presented. Experimentally, such a disorder is difficult to avoid, thus the importance to evaluate its influence on the device performance. Finally, Chapter 8 contains the conclusion and outlook of my thesis work.
Table of contents :
1.1 Trends of micro/nanoelectronics
1.2 Power consumption issues
1.3 Tunnel field-effect transistors
1.4 Quantum transport simulations
2 Brief Introduction to 2-D Materials
2.1 History of 2-D material research
2.2 Basics of 2DMs
2.2.1 Electronic properties of graphene
2.2.2 Crystal structures of other 2DMs
2.2.3 Electronic properties of 2-D TMDs
2.3 Synthesis of 2DMs
2.3.1 Mechanical exfoliation
2.3.2 Liquid-phase exfoliation
2.3.3 Chemical vapor deposition
2.3.4 Molecular beam epitaxy
2.4.1 Digital applications
2.4.2 Analog and high-frequency applications
2.4.4 Flexible electronics
3 Quantum Transport Model
3.1 A brief review of quantum mechanics
3.1.1 Second quantization
3.1.2 Field operators
3.1.3 Basis transformation
3.1.4 The density operator
3.1.5 Hamiltonian operator
3.1.6 Schrödinger equation
3.1.7 Evolution operator and time-ordering
3.1.8 Heisenberg picture
3.1.9 Contour ordering
3.2 Non-equilibrium Green’s function formalism
3.2.1 Definition of Green’s function
3.2.2 Equation of motion
3.2.4 Other Green’s functions
3.2.5 Steady-state condition
3.3.2 Local density of states
3.4.1 Electron-electron interaction
3.4.2 Electron-phonon interactions
4 Implementation of Quantum Transport Model
4.1 NEGF for layered structures
4.1.1 Semi-infinite leads
4.1.2 Recursive algorithm for device region
4.1.3 Phonon self-energies
4.2 Adaptive energy integration
4.3 Structure of the codes
5 Vertical Tunnel-FETs based on 2-D materials
5.1 Device description
5.2 Calibration of the model
5.3 Results and discussion
5.3.1 Role of doping and back-gate potential
5.3.2 Role of top gate extension region
5.3.3 Effective mass
5.3.4 Scalability of device
5.3.5 Delay and energy metrics
6 Van der Waals Tunnel-FETs: 3-D quantum-transport simulations
6.1 Device description
6.2 Simulation model
6.2.1 Model Hamiltonian
6.2.2 Calibration of tunneling coefficient
6.2.3 Transport model
6.3 Results and discussions
6.3.1 Effect of the top gate extension
6.3.2 Effect of the overlap length
6.3.3 Effect of back-oxide thickness
6.3.4 Effect of inelastic scattering
6.3.5 Large overdrive regime
6.4 Comparison of delay and energy metrics
7 Impact of rotational misalignment on the performance of vdW-TFETs
7.1 Simulation model
7.2 Results and discussions
7.2.1 Effect of rotation angle
7.2.2 Effect of phonons
8 Conclusion and Outlook