In depth characterization of carrier transport in 14nm FD−SOI CMOS transistors

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Advanced CMOS technology

In order to suppress the short channel effects and hot carrier effects, and keep the de-vices scale down, the device channel engineering was introduced such as lightly doped drain (LDD), pocket or halo implant. Furthermore, many kinds of technologies have been introduced like multiple gate device, high−k and metal gate, SOI device, strain engineering and alternative channel engineering. Fig. 1.3 is the overview of advanced CMOS technology [10,12].

High−k and Metal gate (HKMG)

As aforementioned, the physical thickness of gate oxide (tox) has been initially de-creased for proper scaling down. However, while silicon dioxide was used as gate oxide, tox reached a limit, around 1.1nm in 2006. Indeed, gate current became unacceptably high as expo-nentially increases with tox reduction. It was a serious problem in terms of device life, standby power consumption and reliability. Thus, the researchers sought other materials with a higher dielectric constant, high−k materials, for increasing tox and replacing SiO2. The equivalent ox-ide thickness can be derived As listed in Table 1.2 [13], various high−k materials have been studied for the future technology. Moreover, as compared to SiO2 and HfO2, there are intermediate solutions for compromising between defect density and high−k, such as oxynitrides (SiON) and hafniumsilicates (HfSiON).
Table 1.2 Properties of the commonly researched high-k dielectric materials from Wilk et al. [13] The metal gate was introduced for blocking of added capacitance from poly−Si since it can act as the additional capacitor which is connected with gate oxide in series. Furthermore, the use of metal gate can suppress dopant penetration through the gate oxide and Fermi level pinning [10]. For controlling threshold voltages, the metal gate electrode should be properly chosen in terms of work function. For the first time, these high−k and metal gate (HKMG) stack were introduced in 45nm−node. In short, Fig.1.4 summarizes why the HKMG technology was needed, and obstacles and solutions of adapting the HKMG to 45nm−node [14].

Strain engineering

The strain engineering in CMOS technology has been introduced to enhance mobility. The mismatch of lattice constants in heterostructures creates local deformations (i.e. compres-sive or tensile strain) [8]. The strain engineering has been a striking method for enhancing the carrier mobility of the CMOS technology at 90nm−node in 2003 and beyond. One general method is to get a tensile strain in Si channel on the relaxed SiGe virtual substrate since SiGe has larger lattice constant than that of Si. As shown in Fig. 1.5, the tensile strain induces varia-tions of the energy band spectrum, which results in reduction of effective electron mass and suppression of inter−band scattering since the curvature of energy band spectrum in k space presents effective mass and there are splits of energy bands. Thus, the tensile strained Si chan-nel can have higher electron mobility than unstrained ones. In the SiGe channel in pMOSFET, the compressive strain has a positive effect on hole mobility [15]. It is worth noting that the strain engineering is the trade−off between mobility enhancement and dislocation formation. In other words, there is a certain limitation in terms of lattice mismatch.

Multiple−gate and tridimensional gate devices

A variety of new gate structures have been introduced with the aim of better control-ling the potential in the channel. They have been proposed in order to eliminate the short chan-nel effects and punch through from source to drain in MOSFETs. Some of these architectures are using independent gates (e. g. double−gate structures). Others are using 3D gates with the aim of wrapping the channel as much as allowed by the fabrication technology such as FinFETs, gate−all−around FETs and Omega gate FETs. They are sometimes named under the general term of “multiple−gate” structures in order to bring attention on the fact that the channel is no longer a simple planar channel but can be viewed as the addition of several channels in parallel, some with different crystal orientations and different dielectric thicknesses for gate control. Re-cently, these device architectures have also been studied with SOI and Silicon substrates as shown in Fig. 1.6 [17].
The multiple gate transistors can bring high on−current, reduction of DIBL and supe-rior properties of on−off operations since the increase of gate number can improve electrostatic control of devices. Quantitatively, it was reported that the planar FD−SOI devices require 1/3 of gate length as a channel thickness (L/3 > tsi) to control short channel effects while the double gate FinFETs need 2L/3 > tsi [10,16]. In the CMOS industry, the FinFET architecture was intro-duced at 22nm−node in 2011 by Intel. Intel expected an outstanding combination of perfor-mance and energy efficiency by 3D tri−gate transistors. In addition, these ultra−low power tran-sistors could be widely used in portable electric devices like cell phones and tablets. There are some challenges in the viewpoint of economic and technological aspects like high process complexity and low yield as compared with FD−SOI and bulk CMOS technologies even though FinFETs have tremendous advantages such as enhancement of performance and varia-bility due to reduction of channel doping concentration and vertical field [17,18].

Silicon−on−insulator architecture

SOI devices were introduced to overcome short channel effects by physically decreas-ing channel thickness since the short channel effects can be efficiently managed by thin Si body layer, roughly less than 1/3 of gate length [16]. Fig. 1.7 displays the difference between bulk transistors and fully−depleted SOI (FD−SOI) devices. One of the remarkable changes between two structures is the thin Silicon layer (Channel) on a buried oxide layer. Depending on the channel layer thickness, we can classify with partial−depleted SOI (PD−SOI) and FD−SOI with thinner channel layers. In order to make a FD−SOI transistor, it should be ensured that the body thickness of is smaller than depletion width [8]: Figure 1.7 Comparative schematic structures of bulk and FD-SOI transistors
In SOI structure, to achieve thin layer of Si with the outstanding crystalline quality is the key point for optimizing FD−SτI transistors, which was solved by a “smart−cut” process of one French company, Soitec in Fig. 1.8.
Figure 1.8 Schematic illustration of the “smart-cut” process [19,20]
There are various benefits of FD−SOI structures; 1) excellent electrostatic control due to ul-tra−thin channel layer, 2) no channel doping required (i.e. less variability and reduction random dopant fluctuation), 3) performance enhancement and VT tenability by back−gate biasing with ultra−thin BOX layer and 4) simple processes. However, the cost of SOI substrates is the draw-back of FD−SOI transistors [21] although wafer cost tends to be an ever smaller fraction of the total cost of a technology and can even be partly counterbalanced by a simpler process flow.

Alternative channel materials

III−V semiconducting materials, such as InP, InGaAs, GaAs and InAS, and Ge are excellent candidates for the channel materials in the next CMOS generation since they have better mobility and less effective mass as compared with Si and SiGe [22]. In addition, for cost reasons, the introduction of these materials should not be performed at the expense of huge changes of CMOS platform and fabrication processes. In order to use them, it is mandatory to obtain at the same time high crystalline III−V and Ge layers, outstanding interfacial quality be-tween channel and oxide, low access resistance and CMOS integration methods.
Figure 1.9 Various example of demonstrating future CMOS technologies: (a) stacking of Si and GaAs nanowire [22], ring oscillator based on (b) graphene [23] and (c) bilayer MoS2 [24], and (d) flexible integrated circuits with CNT [25]
As shown in Fig. 1.9, Carbon based materials (i.e. CNT and graphene), nanowires and 2D transition metal di−chalcogenides (TMDs) such as MoS2 and WSe2 are another route which has recently started to be explored [22−25]. Even though these materials require a number of studies in term of reproducibility and optimization before they can be used in the industry, they have a potential for future technologies such as flexible and transparent devices.

Devices under study

In our study, the devices under test were fabricated by STMicroelectronics using their 14nm−node technology [26−28]. UTBB FDSOI devices with high−k and metal gate were made on (100) SOI wafers with 25nm BOX. The body thickness was thinned down to 7nm for the undoped channel. The UTBB devices can provide outstanding electrostatic control as well as performance enhancement and a switching variability by back-biasing. For the PMOS devices, SiGe channel layers were fabricated by the condensation method (with 10%, 13%, 15% and 20% of Ge) in order to achieve better hole transport properties [29,30]. In our devices, the gate−oxide stack consists of high−k gate dielectric (HfSiτσ) on top of SiON interfacial layer, with an equivalent oxide thickness (EOT) of 1.4nm for GO1 and 4.0nm for GO2 since there is intentional thicker interfacial layer (Iδ) between the high−k layer and channel in Gτ2 devices, while other characteristics of the gate stack remained unchanged as shown in Fig 1.10(a).
τn−mask gate length (δM) ranged from 10 m to γ0nm for Gτ1 devices and from 10 m to 100nm for GO2 devices. The information of GO1 and GO2 devices is summarized in Table 1.3.
As shown in Fig. 1.10(b), the transport characteristics of GO2 devices displays better performance than them of GO1 devices with similar channel lengh (cf. the extraction method-ology and process can be found in Chapter 2.1 and 4.3). It might be due to the distance between channel and high-k layers, which caused by different IL thickness. The various mobility anal-yses were conducted in order to prove it, which are demonstrated in Chapter 4 to 6.

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Dissertation scope and outline

The work described in this dissertation has been mainly carried out at IMEP−LaHC laboratory, with the support of the REACHING 22 CATRENE and Places2Be ENIAC Europe-an projects under Grant Agreement No. CT208 and JTI 325633.
The aim of this thesis is to investigate the electrical properties of 14nm−node FD−SOI CMOS transistors, which is the one of most promising candidates for adoption in sub−20nm CMOS technology nodes because of their interesting potentialities, such as superior electrostat-ic integrity, low variability and so on.
Chapter 2 introduces the main parameters which are used to investigate final device characteristics as well as their extraction methodologies. These parameters can be utilized with the base of device evaluation and modeling. In addition, the principle of magnetoresistance (MR) effects and low frequency noise are described.
Chapter 3 describes the split CV method and how it recovers its full potential with UTBB FD−SOI transistors. We show how it enabled us to extract geometrical parameters relat-ed with whole vertical FD−SOI stack as well as complementary information on back−plain doping concentration. 1D TCAD simulations were carried out for validation and a new correct-ed coupling capacitance model was developed in support.
In Chapters 4 and 5, transport properties in ultra−scaled FD−SOI transistors were studied. The different scattering mechanisms were de−correlated by varying temperature from 77K to 300K.
Chapter 4 compares transport in devices that defer by their gate stacks. The additional scattering times associated to the introduction of the high−k dielectric layer were identified. Temperature dependence of the additional mobility was clarified with in−depth study of the role of the different scattering mechanisms. Furthermore, carrier mobility reduction in short channel devices was intensely characterized. It can originate from additional scattering mechanisms induced by process−induced defects o near source and drain.
In Chapter 5, we added the interface coupling condition, which is a combination of front gate and back gate biasing, to cryogenic operation. It was possible to tune the vertical po-sition of the channel depending on coupling conditions, and we analyzed the influence of this tuning on transport characteristics and mobility enhancement of mobility both quantitatively and qualitatively in long channel devices. The results obtained in short gate devices demon-strated a weaker mobility improvement with back gate biasing. This was found consistent with the fact that transport properties would then be governed by process induced defects distributed around source and drain regions. As compared to NMOS, PMOS transistors with short channel show the surface−like behavior.
Chapter 6 analyzes geometrical magnetoresistance (MR) effects on ultra−scaled FD−SOI devices. The transport characteristics of transistors with an undoped channel was shown from weak inversion regime to strong inversion regime with the advantage that MR ef-fect brings information about transport in the sub threshold regime, while this is out of the range of validity of other extraction methods. For the first time, we applied interface coupling conditions to MR mobility measurements in order to further assess the role of the high−k/metal gate stack on transport properties and to analyze back bias induced mobility variations, depend-ing on temperature range. In addition, we revealed that the critical gate length which is used to characterize mobility degradation at short gate length can be overestimated by using low field mobility (µ0) at low temperature due to a lack of ability of the Y−function method to capture unscreened Coulomb scattering.
We also proved usability of MR mobility characterization from the linear regime of operation to saturation. Besides, a new physical compact model for MOSFET drain current un-der high field transport was developed. The non−stationary and ballistic transport properties of this technology were investigated based on saturation velocity.
Chapter 7 analyzes low frequency (LF) noise behavior of the CMOS technology at 14nm−node with FD−SOI. The 1/f noise behavior was well explained with the carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model, which is grounded on the trapping and de−trapping of free carriers at interfacial layers (i.e. at the interfaces between channel and gate dielectric or BOX) and the correlated changes in Coulomb scattering induced by variations in trapped charges. In addition, we confirmed that CNF with CMF model can ful-ly reproduce LF noise properties from linear to saturation regime.

Table of contents :

Chapter 1 Context of the work
1.1 The context of CMOS technology
1.1.1 CMOS scaling down and Short channel effects
1.2 Advanced CMOS technology
1.3 Devices under study
1.4. Dissertation scope and outline
Chapter 2 Theoretical and experimental backgrounds
2.1 Parameter extraction methods for MOSFETs
2.1.1 Mobility
2.1.2 Series Resistance from the Y−function method
2.1.3 Threshold voltage (VT)
2.1.4 Subthreshold swing (SS)
2.2 Magnetoresistance
2.2.1 Principle of magnetoresistance mobility extraction
β.β.β Comparison between 􀈝eff, 􀈝H and 􀈝MR
2.3 Low frequency noise
2.3.1 Fundamental noise sources
Chapter 3 Full split C−V method for parameter extractions
3.1 Introduction
3.2 Experiment details
3.3 Results and Discussions
3.3.1 Refinement of gate−to−channel capacitance analysis
3.3.2 Gate−to−bulk capacitance exploitation in UTBB FDSOI
3.4 Conclusions
Chapter 4 In depth characterization of carrier transport in 14nm FD−SOI CMOS transistors
4.1 Introduction
4.2 Experiment details
4.3 Results and Discussions
4.3.1 General transport characteristics of NMOS devices and methodologies
4.3.2 Transport properties of PMOS devices
4.4 Conclusions
Chapter 5 Low temperature characterization of mobility in 14nm FD−SOI CMOS devices under interface coupling conditions
5.1 Introduction
5.2 Experiment details
5.3 Results and Discussions
5.3.1 Long channel
5.3.2 Gate−length variations
5.3.2 Short channel in interface coupling conditions
5.4 Conclusions
Chapter 6 Magnetoresistance mobility characterization in advanced FD−SOI transistors
6.1 Characterization of magnetoresistance in linear regime of FD−SOI nMOS devices
6.1.1 Introduction
6.1.2 Experiment details
6.1.3 Results and discussions
6.1.3.1 μMR extraction in long channel at 300K
6.1.3.2 Influence of temperature and gate length variations
6.1.3.3 Additional mobility induced by high−k layer
6.1.3.4 Mobility degradation factor
6.1.4 Conclusions
6.2 Experimental and theoretical investigation of magnetoresistance from linear to saturation regime in 14−nm FD−SOI MOS devices
6.2.1 Introduction
6.2.2 Experiment details
6.2.3 Physical compact model of high field transport with magnetoresistance effect
6.2.4 Results and discussions
6.2.4.1 μMR extraction procedure
6.2.4.2 Modeling of I−V and 􀈝MR in all operation regimes
6.2.4.3 Carrier velocity extraction
6.2.4.4 Comparative analysis of carrier velocity
6.2.5 Conclusions
Chapter 7 Low−frequency noise characterization of 14nm−node FD−SOI CMOS transistors
7.1 Introduction
7.2 Experiment details
7.3 Results and Discussions
7.3.1 Noise characterization in the linear regime
7.3.2 Noise characterization from the linear to saturation regime
7.4 Conclusions
Chapter 8 Conclusions

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