Low-frequency noise in Ψ-MOSFET

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The state-of-art in SOI electrical characterization

Accurate electrical characterization techniques are required to monitor the SOI material quality before pursuing device fabrication process. High transistor performances can be expected only if the carrier mobility in the top silicon film is high and the density of defects at Si film-buried oxide interface is low. In this context, we review here the electrical methods for SOI.
The simplest way to investigate the electrical properties of a material is the 4-probe resistivity measurement. In case of SOI, four needles are directly placed on the top surface of the Si film. A current I is imposed between the two external probes and the potential difference between the two inner probes is measured (ΔVdiff) (Figure II-1). Knowing the inter-probe distance (d), it is possible to directly compute the material resistivity [56]:  2 d F Vdiff (II.1).
where F is a correction factor taking into account the probe location with respect to the sample edges, the sample thickness and the probe diameter. Equation (II.1) is only valid if all the needles have the same inter-probe distance d [56]. In case of large semiconductor samples, where the probes are placed far from the edges and in-line configuration is used (see Figure II-1), Eq. (II.1) can be re-written as a function of the sheet resistance RSH:  4.532 t  Vdiff  t  R (II.2)
where tSi is the silicon film thickness. The carrier mobility can be determined if the doping level is known. However, with this configuration the interface traps density, that qualifies the quality of the BOX-film interface, cannot be measured.

Principle of Ψ-MOSFET and parameter extraction methods

A detailed description of the Ψ-MOSFET and extraction methods for electrical parameters (μ, Dit) from ID-VG characteristics will be provided in this section.
The pseudo-MOSFET configuration with pressure probes does not need contact process. Nevertheless, in order to avoid parasitic leakage currents, the SOI wafer needs a lithography step followed by etching to create square silicon islands (mesas) separated by 2 mm oxide (Figure II-3a). L is the side size of a mesa. These mesas define the dies or the tested regions on the SOI. Most of the analyses were performed on structures with 25 mm2 effective area (i.e., the mask size was 5 mm x 5 mm). However, other areas are available: 4.4 mm2, 9.6 mm2, 16.8 mm2 and 65.6 mm2. Their use for some specific tests will be clearly indicated in the manuscript.
o Passivated samples: the top silicon surface is covered with 4 nm dry silicon dioxide.
o Non-passivated samples: native oxide is present on the top of the Si layer.
The buried oxide will be labeled BOX and its thickness tOX. The substrate of the SOI structures is
made of p-type NID silicon.

Impact of measurement

In this section we discuss the precautions on the measurement setup that may reduce parasitic effects. The importance of choosing good measurement times is presented in Sec. II.3.1. The role played by the back contact is addressed in Sec. II.3.2, while the impact of adjustable pressure probes on the characteristics is pointed out in Sec. II.3.3. Section II.3.4 shows the role of the quality of the top silicon film surface.

Measurement time setup

In order to avoid transient effects and reduce noise, some measurement parameters have to be optimized [33]:
o Hold time: it is the time before starting the first measurement point and it must be long enough so that the structure is in equilibrium conditions at the beginning of the characterization. Used values range: 1-100 s.
o Delay time: it is the time between two consecutive measurement points and it must be long enough to avoid any transient effects due to out-of-equilibrium state. A too long delay time can stress the device.
All our measurements were obtained using a delay time between 0.4 s and 2 s.
o Integration time: the value obtained for each bias point is computed by integrating several measurements performed by the instrument at the same biasing condition. “Short” integration time means very short integration time range. The analysis is fast but usually the curves are noisy due to trapping/detrapping phenomena induced by surface defects. The use of “long” integration time reduces the noise on the characteristics becaue the structure is close to equilibrium condition; but the measurement is more time consuming. In this work, “medium” integration time was used for SOI structure with tSi = 88 nm, while “long” integration time was adopted in case of ultra-thin Si layers (tSi < 20 nm).

Quality of back contact

In Ψ-MOSFET configuration, VG is directly applied on the structure through the chuck. Hence, the quality of the “back contact” (contact between the back of the SOI substrate and the metallic chuck) may affect the obtained characteristics. This problem never arises in case of fully fabricated transistors, because metallic contacts are used.
Two different cases will be investigated:
o Air contact: the wafer is just placed on the metallic chuck. No particular precautions are used to improve the contact.
o Vacuum contact: a vacuum system is used to “stick” the SOI to the metallic surface. This avoids any possible parasitic contributions due to poor contact.
Figure II-8a shows the drain current versus gate bias on SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. The top surface was non-passivated. The characterization was performed with (empty symbols) and without (plain symbols) vacuum system. The results obtained on SOI structure with the same tOX but thinner silicon layer (12 nm) are presented in Figure II-8b. Variation of VT and Ss are obtained in both cases, and there are stronger for the thinner silicon film. Vacuum system will be always used to avoid parasitic effects. In the chapter of split-CV measurements we will show that the vacuum contact is even more critical.

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Role of the probes

The probes have an important role on the obtained Ψ-MOSFET characteristics. It was proved that RSD is directly related to the probe pressure [65]. Furthermore, the probe position on the silicon surface can affect fG value [67], [68]. Several aspects will be addressed to clarify these effects and how they limit the extraction.
The Jandel® station has four in-line probes. In Ψ-MOSFET configuration only two probes are used, thus it is possible to choose among the four needles. We mainly considered the case with d = 1 mm.
Figure II-9a shows the measured ID as a function of VG using different needles. Curves match for low VG but for very large gate bias some differences are present. In this region, RSD (which is probe related) becomes relevant, inducing ID variations. The corresponding Y functions are shown in Figure II-9b. The impact of access resistance is removed in this case (see Eq. (II.6)) and the curves superpose. Thus, the choice of the probe is not critical in case of ID-VG characterization analyzed using the Y function.

Reproducibility of tests

In pseudo-MOSFET configuration, the source and drain contacts are obtained using probes directly placed on top of the silicon surface. This can be a new source of variability added compared to standard transistors with fabricated metal contacts. In this section we investigated the reproducibility of material characterization (i.e., parameter extraction) obtained using the Y function method on static ID(VG) curves. We also defined the order of magnitude of error bars of calculated μ0 and VT.
The fitting range of Y function can affect the obtained results: a maximum variation of ± 4.5 % is obtained for μ0 and ± 3 % for VT.
Figure II-13 shows the extracted low-field mobility (plain symbols) and threshold voltage (empty symbols) for different dies present on the same SOI wafer. The maximum incertitude of μ0 is around ± 5 %. Lightly lower variation is found for VT (± 3 %). Thus, total error bars around 15 % represent a good estimation for the measurement technique.

Table of contents :

Chapter I: General introduction
I.1 MOS transistors: state of art and trends
I.2 SOI substrates
I.3 Objectives and organization of the thesis
Chapter II: Pseudo-MOSFET for SOI characterization
II.1 The state-of-art in SOI electrical characterization
II.2 Principle of Ψ-MOSFET and parameter extraction methods
II.3 Impact of measurement
II.3.1 Measurement time setup
II.3.2 Quality of back contact
II.3.3 Role of the probes
II.3.4 Passivated top silicon film
II.4 Extension of Ψ-MOSFET to new materials: III-V-on-insulator
II.4.1 Material characterization before bonding
II.4.2 Ψ-MOSFET with pressure probes on III-V-on-insulator (III-V-OI)
II.4.3 Ψ-MOSFET with metal contacts on III-V-OI
II.4.4 Preliminary results of III-V transistors
II.5 Conclusions and perspectives
Chapter III: Split-CV in Ψ-MOSFET
III.1 Introduction
III.1.1 Split-CV in MOSFET devices
III.1.2 Split-CV in pseudo-MOSFET configuration: state of the art
III.2 Effective surface and improved measurement setup
III.2.1 Dependency of Seff
III.2.2 Improved measurement setup
III.2.3 Robustness of the technique (probe effects)
III.3 Frequency effects
III.3.1 Model derivation
III.3.2 Model validation
III.3.3 Dit signature
III.4 Conclusions and perspectives
Chapter IV: Quasi-static capacitance in Ψ-MOSFET
IV.1 Introduction: quasi-static CV in MOS structures
IV.2 Quasi-static capacitance in pseudo-MOSFET
IV.2.1 Basics of QSCV for Ψ-MOSFET
IV.2.2 Comparison with LCR meter measurements
IV.3 Impact of measurement parameters
IV.3.1 Impact of back contact quality
IV.3.2 Impact of the probes
IV.3.3 Impact of scan direction
IV.4 Dit model
IV.4.1 Model derivation
IV.4.2 Model validation
IV.5 Dit extraction procedure
IV.6 Characterization of non-passivated samples
IV.6.1 Traps charging procedure
IV.6.2 Example of Dit extraction for non-passivated samples
IV.7 Surface potential computation
IV.8 Comparison of Dit profiles for different samples
IV.9 Conclusions and perspectives
Chapter V: Low-frequency noise in Ψ-MOSFET
V.1 Introduction to low-frequency noise
V.1.1 Noise parameters: the Power Spectral Density of a signal
V.1.2 LFN in MOSFETs
V.1.3 State of art of LFN in pseudo-MOSFET
V.2 LFN characterization in Ψ-MOSFET
V.2.1 Measurement setup
V.2.2 Reproducibility issues
V.2.3 Probe pressure impact
V.2.4 Impact of inter-probe distance and die area
V.3 LFN in inhomogeneous material
V.3.1 Physical model
V.3.2 Computation of LF-noise
V.4 Effective surface in LF-noise
V.4.1 Why an effective surface?
V.4.2 Quantification of effective surface
V.5 Probe penetration effects
V.5.1 Experimental evidences
V.5.2 Computation of induced defects by probe penetration
V.6 Conclusions and perspectives
Chapter VI: General conclusions and perspectives
VI.1 Conclusions
VI.2 Perspectives
Appendix I
Van Der Pauw experiments
Hall effect measurement
Table of Acronyms
Table of Constants
Table of Symbols


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