Millimeter Wave Device Measurement and Characterization in Silicon Integrated Circuits

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Slow-Wave Coplanar Waveguide (S-CPW) Transmission Line

S-CPW was introduced [11]-[15] to miniaturize and to improve the quality factor (Q-factor) of the passive structures. The major drawbacks of the microstrip transmission lines and the CPW transmission lines in the silicon-integrated technologies are their size and poor quality factor. There are different approaches that have been done to miniaturize the transmission lines, by using high permittivity substrates and lumped or semi-lumped components [15], but these are restricted to apply in the silicon integrated technologies. In the silicon integrated technologies the classical transmission lines such as CPW have high losses when the frequency increases, due to its dielectric loss effects in the low-resistivity silicon substrate and the conductive loss. Concerning microstrip lines, losses are limited because, the ground plane prohibiting the electromagnetic field to go through the low-resistivity substrate. Nevertheless, due to a low effective dielectric constant, a low Q- factor can be achieved.
The standard approach to miniaturize the transmission line is by increasing relative dielectric permittivity εr of the substrate, which eventually reduces the phase velocity, 𝑣𝑝=𝑐√𝜀𝑟⁄. The “Slow wave” transmission line uses the principle of separating the electric and magnetic energy, to reduce the phase velocity instead of using a high dielectric permittivity εr substrate. S-CPW are based on conventional CPW with floating metallic strips underneath the line as shown in Figure 1.1.
Consider a classical S-CPW configuration, where W is the width of the signal strip G is the gap between signal and ground, Wg is the ground plane width, SL is the floating strips length, SS is floating strips space and h is dielectric thickness between floating strips and the CPW lines.
The electric and magnetic field propagation modes of S-CPW simulated using a 3D electromagnetic solver Ansys HFSS [16] are shown in Figure 1.2. In Figure 1.2 signal strip is in the center with two ground strips on both sides, like conventional CPW and with horizontal floating strip to reduce the phase velocity.
From the S- CPW line in Figure 1.2(a), the fingers of length SL with a space of SS are created as a shield against the low resistivity substrate. If we use a whole ground instead of floating fingers (such as microstrip lines), we induce eddy currents in the thin lower metal layer and it would increase the significant conductive loss. In S-CPW, the transversal arrangement of the floating fingers prevents the currents flowing longitudinally to the signal propagation. Moreover, if fingers gap SS is optimized the electric field is confined between the signal and grounds of S-CPW. Since there is no electric field in the lossy silicon substrate, the losses due to the low resistivity silicon substrate are reduced. Hence S-CPW losses are comparable to microstrip line losses and lower than CPW ones. Finally, the floating shield results in the significant increase of the capacitance per unit length Cl compared to CPW. As shown in Figure 1.2(b) the magnetic field passes through the patterned ground, hence the inductance per unit length Ll is quite unchanged compared to CPW lines.
Thanks to the increase of the capacitance, the phase velocity in the S-CPW (1.2) decreases as compared to the CPW transmission line. Therefore, it is “Slow-Wave” coplanar waveguide. Due to this we can obtain (1.2) a high relative effective permittivity.

Motivation: Applications at Millimeter-Wave Frequencies and Above

The transmission lines are an essential passive component for any device/application from the low frequency to the high frequency. Concerning the applications of millimeter and sub-millimeter wave frequency circuits (Video-streaming 57-66 GHz, 76- 81 GHz automotive radar, medical imaging 140 GHz, etc.) the need and characterization of the transmission lines are very important. Transmission lines are used in wide variety of passive and active applications such as interconnection for the circuits, calibration and de-embedding circuits from vector network analyser (VNA) to devices, filters, baluns, power dividers, couplers, power amplifiers, detectors, mixers, antennas, trans receivers etc. They serve a major role in every two ports and multiport devices.
Some applications/devices using microstrip transmission lines and CPW Transmission lines are shown in Figure 1.3. Figure 1.3 (a) shows 60 GHz MM BPF[18] using a microstrip lines, Figure 1.3(b) is a Power Amplifier matching network using Microstrip Stubs [21], Figure 1.3(c) shows a chip microphotograph of the 30-GHz CPW filter[19] and Figure 1.3(d) shows a chip microphotograph of the 3-stage 60-GHz CPW amplifier [19].
Since S-CPW transmission lines have many advantages over microstrip and CPW transmission lines, they can be widely used in many passive and active circuits/applications. IMEP-LAHC is developing applications specifically based on S-CPW topologies. Figure 1.4(a) shows Band Pass Filter (Dual Behaviour Resonator (DBR) type) which uses S-CPW lines, [20], further examples with the power splitter and power dividers with S-CPW transmission lines [22], [15], which are shown in Figure 1.4(b) and Figure 1.4(c) and finally the matching network of a power amplifier is changed from microstrip to S-CPW [21] shown in Figure 1.4(d).
The motivations of this Ph.D. thesis are to develop the de-embedding methods to characterize the transmission lines, especially, S-CPW at millimeter wave and sub-millimeter wave frequencies. Also analyse the various issues for S-CPW, CPW and microstrip transmission lines at millimeter wave and sub-millimeter wave frequencies and provide the solutions to overcome it [3]-[15].

Electromagnetic Modeling and Measurement Uncertainties

Considering the transmission line modeling, circuit designers use electrical scalable models (Using Agilent ADS or other circuit simulators) or electromagnetic (EM) models (Ansys HFSS, CST Microwave Studio, COMSOL Multiphysics…) to understand its characteristics.
Considering electrical scalable model and with its optimization, it is difficult to analyse the design problems at higher frequencies, especially when the targeting applications are in millimeter and sub-millimeter wave frequencies. The electrical scalable models are easy to use for designing and optimizing transmission lines. But considering all the parasitic and coupling elements of a transmission line model, especially at the millimeter wave frequency range, it is difficult and in many cases not even possible. It has the disadvantages of analysing proper electromagnetic behaviour of the transmission lines and difficulty to understand the radiation effects, higher order transmission modes, etc. [23]. Therefore, we need to have an EM (electromagnetic) model to characterize them properly for the different applications [24]. EM modeling helps to analyse all the physical effects of passive structures/devices such as losses, fields, radiation effects, higher order transmission modes, etc. The EM simulation is time consuming, but it gives more accurate results than the electrical scalable models.
Many 3D full wave Electromagnetic simulators are commercially available (Ansys HFSS, CST Microwave Studio, COMSOL Multiphysics…). These simulators use different mathematical techniques to solve and characterize electromagnetic structures. We utilize an industry-standard simulation tool Ansys HFSS (High Frequency Structure Simulator) [16]. This software is a 3D full wave frequency domain electromagnetic field solver based on the finite element method (FEM). HFSS automatically generates mesh and solves Maxwell’s equations at several nodes of the meshing; also it allow us to generate our own strict meshing for the electromagnetic structures.

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Table of contents :

General Introduction
Outline and aim of the thesis
Millimeter Wave Device Measurement and Characterization in Silicon Integrated Circuits
1.1 State of the Art and Problem Description
1.1.1 Transmission Lines for Millimeter-Wave and Sub-Millimeter-Wave Frequencies and Applications
1.1.2 Slow-Wave Coplanar Waveguide (S-CPW) Transmission Line
1.1.3 Motivation: Applications at Millimeter-Wave Frequencies and Above
1.1.4 Electromagnetic Modeling and Measurement Uncertainties
1.1.5 De-embedding and Challenges
1.1.6 De-embedding with and without Interconnect/Accesslines
1.1.7 Bended-Accessline De-embedding
1.1.8 Excessive Losses at Millimeter Wave Frequencies and Above
1.1.9 Other Measurement Challenges
1.1.10 Conclusion of State of the Art and Problem Description
1.2 On-Wafer Measurement and Challenges at Millimeter Wave Frequencies
1.2.1 Calibration and Challenges
1.2.2 RF Probes
1.3 Conclusion
1.4 References
De-embedding Methods
2.1 Classification of De-embedding Methods
2.1.1 Lumped Equivalent Circuit Model
2.1.2 Cascaded Matrix Based Models
2.1.3 Cascaded Matrix with Lumped Equivalent Models
2.1.4 Conclusion and Further studies of Classification of De-embedding Methods
2.2 BiCMOS 55 nm Silicon Technology
2.3 Proof of Concept with ADS
2.3.1 Pad-Acceslines Parasitics Models
2.3.2 De-embedding Structures: Known Parasitics De-embedding
2.3.3 Analysis of Lumped Equivalent Circuit Model De-embedding Methods
2.3.4 Analysis of Cascaded Matrix Based Model De-embedding Methods
2.3.5 Analysis of Hernandez Method
2.3.6 Analysis of Cascaded Matrix with Lumped Equivalent Model De-embedding Methods
2.3.7 Conclusion of Proof of Concept with ADS
2.4 Proof of Concept with HFSS
2.4.1 Parasitics Model: Unknown Parasitics De-embedding
2.4.2 De-embedding Structures
2.4.3 Benchmarking and Comparison of De-embedding Methods
2.5 Conclusion
2.6 References
Half-Thru De-embedding
3.1 Half-Thru De-embedding
3.2 Theoretical Analysis
3.3 Proof of Concept with Known Electrical Model Parasitics
3.3.1 Simulation and De-embedding Results with Known Parasitics using ADS
3.3.2 Conclusion of Proof of Concept with ADS
3.4 Proof of Concept with Unknown EM Model Parasitics
3.4.1 Measurement Setup and De-embedding Structures
3.4.2 Simulation and Results: Benchmarking and Comparison with TRL
3.4.3 Simulation with and without accessline
3.4.4 Effect of the Load Value Analysis
3.4.5 Comparison with Effect of the Characteristic Impedance of the Line of the TRL
3.4.6 Conclusion of Proof of Concept with HFSS
3.5 Extraction of the Load value for Half-Thru De-embedding
3.5.1 Open De-embedding
3.5.2 Open-Short De-embedding
3.5.3 Load value extraction with Kolding’s Method
3.5.4 Simulation and Results of Load Extraction Methods
3.5.5 Half-Thru De-embedding with Different Load Extraction Methods
3.5.6 Conclusion of Extraction of Load Value for Half-Thru De-embedding
3.6 Simplified Half-Thru De-embedding: Thru-Load De-embedding
3.6.1 Simulation and Comparison with Half-Thru De-embedding
3.7 Conclusion
3.8 References
Measurements and Electromagnetic Modeling Analysis of De-embedding Methods
4.1 AMS 0.35 μm CMOS Technology
4.2 Fabrication Map
4.3 Comparison of Half-Thru De-embedding and TRL
4.3.2 Load value Extraction
4.3.3 Comparison of Half-Thru De-embedding and TRL
4.3.4 Analysis of Excessive loss in S-CPW of 65 Ω and 30 Ω
4.3.5 Impact of EM-Model in De-embedding
4.3.6 De-embedding: CPW Transmission Line as DUT
4.3.7 Conclusion of Comparison of Half-Thru De-embedding and TRL
4.4 EM-Model Issues and Analysis
4.4.1 On-wafer: Fabricated Transmission Lines
4.4.2 EM – Model of Measured CPW transmission line
4.4.3 EM – Model of Measured CPW transmission line with adjacent cells
4.4.4 EM – Model of Millimeter Wave Probe
4.4.5 EM – Model of measured CPW transmission line with Millimeter Wave Probe Model and Adjacent Cells
4.4.6 De-embedding with the realistic EM- Model
4.4.7 Reasons of Excessive Loss
4.4.8 Other Possible Losses
4.4.9 Conclusion of EM-Model Issues and Analysis
4.5 Solutions
4.5.1 Conclusion of On-wafer Measurement Issues and Possible Solutions
4.6 Half-Thru De-embedding and Thru-Load De-embedding Analysis
4.6.1 De-embedding with Different Length of the DUT
4.6.2 De-embedding with Different Characteristic Impedance of DUT
4.6.3 Half-Thru De-embedding with Different Load Extraction Methods and with Different Load Values
4.6.4 De-embedding with Different Accessline Topology
4.6.5 Comparison and Benchmarking of de-embedding methods
4.6.6 De-embedding with Bended-Accessline Model
4.6.7 Conclusion of Half-Thru De-embedding and Thru-Load De-embedding Analysis
4.7 Half-Thru de-embedding and Thru-Load de-embedding in B55 nm Technology
4.8 Conclusion
4.9 References
Conclusion and Perspective


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