Overview of Semiconductor Industry
After the first demonstrations of “Bipolar-Junction-Transistor (BJT)” developed by W. Shockley, J. Bardeen, and W. Brattain in 1947 and “Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)” realized by Labate, Kahng and Atalla at Bell Labs by in 1960s,[1-5] a silicon based transistor is dramatically developed as a fundamental building block of integrated circuits (ICs) up to a few tens of nanometer scale device.[4, 6, 7]
Figure 1-1 Photographs of the firstly developed (a) BJT (in 1947), (b) MOSFET (in 1960), and (c) IC (in 1961), respectively.
Besides, the market demands for high memory density and versatile functionality of ICs are also rapidly increased after the realization of personal computer, smart applications such as iOS and Android based smart phone, a high resolution digital camera, and Nintendo Wii etc. To satisfy these needs, the semiconductor technology has been focused on scaling down its size to follow “Moore’s law” reported in 1975, which predicted that the number of transistors on a chip would double about every two years. This scaling down trend has been successfully continued up to 22nm technology referring to ITRS report as seen in Fig 1-2, and recently Intel manufactured a processor containing 1.4 billion transistors in 160mm2 area as displayed in Fig.1-3.
Figure 1-2 2011 International Technology Roadmap of Semiconductors (ITRS)-Dynamic Random Access memory (DRAM) and Flash memory half pitch trends. [http://www.itrs.net/]
Figure 1-3 Intel’s 22nm technology for FinFET structure and Intel core i7-3770K (22nm Ivy Bridge) [http://newsroom.intel.com/docs/DOC-2032]
As the device size is shrunk, it enables to drive many advantages such as increasing an integration density in a chip, enhancing a switching speed, increasing a frequency of amplifier, a lowing power consumption and cost per wafer. Especially, the switching speed enhancement is very important performance in digital and information era. This can be achieved by reduced geometrical effects arisen from the mainly reduction of the gate oxide capacitance (Cox=0rLW/tox, where tox is the oxide thickness, L is the gate length, W is the gate width, and0 andr are the vacuum and the relative permittivity, respectively) by the factor of the scalingratio, since the circuit RC delay () is directly proportional to on-current (=CoxVDD/Ion, VDD is the supplying voltage, and Ion is the operating current when the gate-to-source voltage (Vgs) is equal to VDD). [4, 9, 10] Details of the constant field scaling rule will be discussed in next sec-tion.
CMOS Scaling Issues and Short Channel Effect
The most ideal strategy of MOSFET miniaturization is simply scaled down of all ge-ometrical parameters and drive voltage to sustain the same internal electric field in the channel as in the long channel device to avoid short channel effects (SCEs).[9, 11] For instance, as illus-trated in Fig. 1-4, to keep the constant value of vertical an lateral electric field, VDD and various device geometrical factors (W, L, and xj) have to be reduced with the scaling factor (), where-as NA should be more heavily doped by factor of to reduce WDep to block the punch-through phenomenon.[9, 11] However, this higher doping concentration again leads to threshold voltage raise (Vth, see details in Ch.188.8.131.52). Therefore, in order to maintain Vth range, tox must be thinner by the factor of to increase the gate controllability. With account for these facts, it can be concluded that all MOSFET parameters are closely interrelated with the scaling factor as sum-marized in Table 1-1.
Figure 1-4 Illustration of scaling parameter of MOSFET.
Table 1-1 MOSFET scaling parameter derived from constant field scaling. [9, 11]
Device scaling has been successfully followed by constant-field scaling law with factor until 2003. However, with decrease of device physical size up to sub tens of nanometer scale, the density and complexity of the integrated circuit (IC) are dramatically increased, and it causes undesired degraded effects, so generally called SCEs, where the gate field no longer has the electrostatic controllability of the channel to turn it off due to the enhanced latter field, eventually leading to the high leakage current and the large power consumption in “stand-by off” state.
Many SCEs have been reported such as drain-induced barrier lowering (DIBL), punch-through, mobility reduction by gate-induced surface field, velocity saturation, im-pact ionization near drain region, and hot-carrier injection etc depending on different phys-ical origins.[9, 12]
1. Punch through can be occurred when the sum of junction width of drain (xjd) and source (xjs) is merged together, i.e., xjd+xjsL. In long channel MOSFET that shows usually xjd+xjs«L, the current can only flow provided that the inversion channel is sufficiently formed by Vgs. However, as the length of device becomes shorten, the driving current is not depending on Vgs but mainly the drain voltage VD. To minimize this, thinner tox to enhance the gate controllability, high substrate doping to reduce depletion width, and shallow junction between such as lightly doped drain (LDD) is used. Likewise, DIBL is closely related with potential barrier, so called built-in potential at the source and drain interface with channel (p-n junction). Since VD the strong latter field in short channel MOSFET enables to de-plete some portion of the channel, the junction barrier between drain and channel can be lowered, eventually MOSFET can flow the current in advance even before Vgs<Vth.
Figure 1-5 Energy-band diagrams at the semiconducting surface from source to drain, for (a) long and (b) short channel MOSFET, respectively.
2. Mobility reduction by gate-induced surface field is usually observed in short channel device with thin oxide layer. Since the carrier has to transport into the very thin and confined inversion layer underneath the gate dielectrics with high perpendicular field to the channel, the scattering caused by surface roughness aris-en from high gate field can be induced the reduction of the mobility. It is therefore evidently dependent on Vgs.[9, 10]
3. Velocity saturation is usually observed when the carrier drift velocity (vd) is satu-rated up to its maximum drift velocity (vdsat) due to the high electric field to the channel. In fact, the drift velocity (vd=E, where E and are the electric field and carrier mobility, respectively) is linearly proportional to E with constant below Ec (Ec is the critical electric field with a value of104V/cm at 300K) in long chan-nel device since E is low enough. However, the size of length becomes shorter, vd is deviates from a linear dependence and eventually is saturated when E>Ec. Hence, the velocity saturation effect has to be taken into account in short channel MOSFET (vd=E/(1+E/Ec) for E<Ec, vd=vdsat107cm/s for E>Ec).
Figure 1-6 Drift velocity (vd) curves as a function of E for silicon and semiconductor.
4. Impact ionization near drain region is occurred especially in N-type MOSFET at the end of pinch off drain region. If electrons have a high kinetic energy in pres-ence of high drain field, it would be accelerated with high gate field and injected into the depletion layer, resulting in generation of electron-hole (e-h) pairs by im-pact ionization as illustrated in Fig. 1-7. The generated electrons will directly go to drain and add to the current, whereas the majority of generated holes can be moved to substrate and even sources in short channel device. This hole current acts it as a n-p-n bipolar transistor, eventually the substantial leakage current will flow through the substrate.
Figure 1-7 Illustration of impact ionization near drain region in N-type MOSFET. happens when the electrons in the channel gain a sufficient kinetic energy in pres-ence of high gate field enough to overcome a silicon-silicon oxide barrier (3.1eV), and they can generate oxide trap charges in dielectric, giving rise to a gate leakage current and trap sites. It will eventually degraded the device performance by in-creasing Vth and impact adversely the gate controllability on the drain current Finally, various SCEs are introduced. However, in order to sustain the continuation of Moore’s law and even more than Moore, many new technologies have been introduced by many researchers such as adopting strained silicon to reduce the effective mass of carriers, thicker high- dielectric materials in conjunction with metal gate to shrink the leakage current, and multi-gate structure to have optimum gate controllability to improve device performance and to minimized SCEs. Actually, this trend can be ultimately faced with physical limitations. However, it will be continuing up to the quantum mechanics governed atomic scale by employ-ing alternative break through approaches. In the next sections, advanced MOSFET technologies will be presented to overcome such aforementioned SCEs.
Advanced MOSFET technology
The physical scaling limitation is almost reached, and particularly the scaling down of tox will be already interfered by quantum mechanical effects such as tunneling and dark space existence.[6, 7, 9] Furthermore, the fabrication optimization in such extremely small geomet-rical volume is challenging as well since the tiny statistical deviation arisen from the device process will lead to the serious performance variability even though it associates with few at-oms in the channel. To overcome SCEs and sustain continuing scaling trend, many new concept devices and optimized fabrication technologies have been suggested as seen in Fig. 1-8. such as silicon on insulator (SOI), multi-gate structure, tunneling FET, channel doping engi-neering, source/drain engineering, high- dielectric stack engineering, 3-dimensional (3D) structure, channel strain engineering, and alternative channel material such as III-V (for N-type) and Ge (for P-type).[7, 9, 15]
Figure 1-8 2012 ITRS “Equivalent Scaling” process technologies timing Overall Roadmap Technolo-gy Characteristics (ORTC) microprocessor unit (MPU)/High-performance ASIC half pitch and gated length trends and timing, and industry “Nodes”. [http://www.itrs.net/]
1. Strained Silicon in n-type MOSFETs were successfully demonstrated at L<70nm in 2001 to improve the speed of CMOS technology.[16, 17] This can be achieved by placement silicon germanium layer with a lager lattice constant under the ac-tive silicon channel as a substrate layer as seen in Fig. 1-9.[16, 18] It induces strain effect in the channel and reduces phonon scattering giving rise to mobility enhancement by modifying the band structure. Especially, the hole mobility also can be improved by increasing fraction of germanium.
Figure 1-9 Illustration of (a) straining of silicon by means of silicon germanium and (b) mechanism of gate stress memorization technique [17, 18]
2. Silicon on insulator (SOI) structure can completely separate a ultrathin film of single crystalline silicon and the bulk substrate by using “Smart Cut” process as shown in Fig. 1-10. It enables to suppress the impact of ionizing radiation effects by a buried oxide layer, large power consumption arisen from parasitic and leakage currents, and various SCEs by successfully eliminating punch-through possibility. These fact results in performance improvements in terms of speed, but some issues are still remained to be solved since there are self-heating problem, floating body effect, and high fabrication cost per wafer etc.[18, 19]
Figure 1-10 Fabrication process of manufacturing ultrathin SOI via Smart Cut process [http://www.soitec.com/en/technologies/smart-cut/]
3. Multi-gate structure (double, triple, quadruple, and gate all around structure) has been considering as a further promising candidate to have the larger immunity for SCEs compared to classical single planar gate devices as presented in Fig. 1-11. It enables to provide several advantages such as enhanced gate controllability, in-creased gate-drive current, reduced subthreshold swing and subsequently sup-pressed gate leakage current, reinforced pinch off effects, and improved process reliability.[9, 17, 18] Consequently, it gives rise to relaxed channel doping concen-tration and vertical field to the channel resulting in improved performance and process variability in terms of better mobility and random dopant fluctuation, respectively. However, there are technological and economical challenges to be em-ployed in practical applications such as Vth modulation and parasitic capacitance arisen from weak body effect and increased layout density. The fabrication cost and process complexity are also challenging to have a compatibility with conven-tional bulk planar CMOS devices.
Figure 1-11 Several types of multi-gate MOSFETs structure.
4. High- and metal gate stack such as hafnium oxide (HfO2) and zirconium oxide (ZrO2) etc as summarized in Fig. 1-12 has been successfully introduced at 45nm
node to suppress the rapidly increased gate tunneling current arisen from very thin tox (less than1nm). Theoretically, it can be achieved by simple capacitance relationship as shown in below expression by ignoring side effects such as leakage current and reliability,
t ox thigh or simply, t high t (1-1),
ox high high ox ( 3.9) ox
whereox and tox (equivalent oxide thickness) are the dielectric constant and thickness of silicon oxide respectively, andhigh- and thigh- are that of high- ma-terials. It allows to have a thicker dielectric thickness to reduce leakage cur-rent while ensuring the same gate controllability. At the same time, in order to cir-cumvent mobility degradation induced by remote Coulomb scattering at the inter-face and Vth pinning, the band-edge work-function metal has to be used as a gate electrode. In addition, the polysilicon depletion effects can be removed by metal gate. However, it contains a high level of interface traps and impurities and thus posing significant performance degradation which should be solved for RF applications.
Figure 1-12 (a) Comparison table of relevant properties of potential candidates of high- dielectric materials and (b) corresponding band offset calculation result.
5. Alternative channel material with high carrier mobility and low effective mass such as III-V semiconductor, GaAs, InP, InGaAs and InAs for n-type and Ge for p-type has been considered as a potential solution to overcome current scaling is-sues.[22, 23] Especially, combination of III-V (for n-type)/Ge (for p-type) on sili-con has been suggested as an ultimate CMOS structure in order to utilize silicon based CMOS platform as presented in Fig. 1-13(a). However, as depicted in Fig 1-13(b), several constrain issues has to be solved to have a compatibility with con-ventional CMOS technology: (1) high crystalline quality of III-V/Ge MOS on a large size of silicon wafer (2) gate insulator engineering with superior interface quality (3) low channel access resistance (4) total COMS integration (5) ultra thin body Ge/ III-V channels to suppress SCEs.[23, 24]
Table of contents :
11B1.1 Overview of Semiconductor Industry
12B1.2 CMOS Scaling Issues and Short Channel Effect
13B1.3 Advanced MOSFET technology
14B1.4 Conclusion and Dissertation Outline
2B2. Electrical characterization of MOSFET
16B2.2 Basic Operation Principle of MOS-FET
17B2.3 Y Function Method
18B2.4 Split C-V Method
19B2.5 Low Frequency Noise Analysis
3. Numerical percolation simulation with SPICE simulator
22B3.2 Percolation Theory
23B3.3 Numerical Percolation Simulation with Floyd’s Algorism
24B3.4 SPICE (simulation program with integrated circuit emphasis) Simulation
4B4. Flat-band voltage and low-field mobility analysis of junctionless transistors under low-temperature
27B4.2 Device Fabrication Process and Electrical Measurement Conditions
28B4.3 Experimental Results and Discussion
29B4.4 Temperature Dependence of Electrical Parameters of Tri-Gate Nanowire JLTs
5B5. Carrier mobility and low frequency noise characteristics of tin-oxide nanowire FET
31B5.2 Device Fabrication Process and Electrical Measurement Conditions
32B5.3 Effective Gate-to-Channel Capacitance Simulation
33B5.4 Mobility Analysis
34B5.5 Low Frequency Noise Characteristics of SnO2 NW-FETs
6B6. Charge transport of quasi-2D random network of carbon nanotube TFTs
37B6.2 Device Fabrication Process and Electrical Measurement Conditions
38B6.3 Static Parameter Extraction
39B6.4 Low Frequency Noise Characteristics
40B6.5 Numerical 2D Percolation Simulation
41B6.6 Effective Gate Coupling Capacitance Model
7B7. Thermoelectric power of single walled carbon nanotube networks
44B7.2 Sample Preparation and Measurement Method
45B7.3 Optical UV-vis-NIR Range Analysis of Precisely Tuned Ratio of Semiconducting and Metallic SWCNTs
46B7.4 Theoretical Modeling with account for the Effect of Junction TEP in Mono-dispersed SWCNT networks
47B7.5 TEP Characteristics of Precisely Tuned Ratio of Semiconducting and Metallic SWCNTs
49BAppendix A. A dual analyzer for real-time impedance and noise spectroscopy of nano-scale devices
10BList of publications