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Modeling of electrical transport in Si and SiC nanowire FET
When the channel length (L) of MOSFET is sufficiently larger than the mean-free-path length ( ) of electrons, as illustrated in Figure 2.1, a first principle semi-classical based on the electronic transport modeling (such as Monte Carlo (MC) simulation  and a full Boltzmann equation (BTE) ) well describes the electrical behavior of devices. However, as the feature size of the MOSFETs enters into the nanoscale (or when L is close to the ), these models are faced with difficulties arising from the quantum mechanical effects. Therefore, full quantum transport approaches, such as the nonequilibrium Green’s function (NEGF) formalism, become necessary to describe the quantum confinement effects and the ballistic transport.
In this chapter, the electronic transport in SiC (or Si) NWFET has been investigated based on the NEGF formalism in the ballistic regime with a diameter below 5 nm. Before delving into details simulation results, I’ll briefly introduce the main features of the simulation models of SiC (or Si) NWFET using the NEGF formalism. And then I’ll show the simulation results of electrical transport of SiC and Si NWs, including the thermoelectric properties.
Our simulation of electrical devices involves a self-consistent simulation scheme between the charge distribution ρ (obtained from Schrödinger equation) and the electrostatic potential (obtained from Poisson equation). To fully realize the self-consistent simulation, we need to understand the two major equations in our simulations.
The calculation of the fundamental physical observables parameters (i.e. charge distribution ρ(r) and current) for a given the self-consistent potential energy USC(r), is obtained by the solution of the time-independent Schrödinger equation (Eq 2.1): = − + S =, Eq 2.1 where H is the Hamiltonian (in parabolic effective mass approximation), ψ(r) is the electron wave function, m* is the position-dependent effective mass tensor, U the conduction band potential energy profile, E the injection energy of the carrier, and r=(x, y, z) is the 3D position vector.
The electrostatic potential is computed through the solution of the Poisson equation. Specially, in order to take into account the non-homogeneities in the simulated structure, we adopted a generalized form for Poisson equation (Eq 2.2): ( ) = − = = − , Eq 2.2 determines the self-consistent potential energy USC(r) ( is the electrostatic potential) for a given charge density ρ(r).
where ε(r) is the position-dependent dielectric constant of the medium, ρ(r) is the charge density. It
which determines the conduction band profile (U ↔ – q , where q is the elementary charge). On the other hand, the electron density depends on the solution of the Schrödinger equation through the square modulus of the electron wave function. The two equations are iteratively solved until a convergence. Thus, a coupling between (Eq 2.1) and (Eq 2.2) is determined and an iterative self-consistent scheme has to be applied to find the solution, as shown in Figure 2.2.
The numerical calculation is starting from an initial guess coming from the solution of the Poisson equation, Non equilibrium Green’s Function formalism NEGF solves the Schrödinger equation under non-equilibrium conditions. NEGF provides an ideal approach for bottom-up device simulations due to the following reasons:
(1) The device can be coupled to contact,
(2) Open boundaries can be rigorously treated,
(3) Atomistic descriptions of devices can be readily implemented,
(4) Multi-phenomena (e.g. tunneling, inelastic scattering) can be included.
In the NEGF formalism, the two main quantities to be calculated are the retarded Green’s function GR, which describes the dynamics of electrons inside the conductor (Eq 2.3) and the lesser-than Green’s function G<, which correlates the electron wave functions (Eq 2.4).
where a matrix notation has been adopted and η+ is an infinitesimal positive value, Hd presents the device Hamiltonian, GR is the retarded self-energy, GA is the advanced Green’s function (which is the Hermitian
adjoint operator of GR) and describes the in-scattering rates including the effect of scattering from both contacts and phonons.
The electrical current (at 300 K) within NEGF formalism is calculated using the following equation (Eq 2.5), = ∫ − , Eq 2.5
where g denotes the degeneration coefficients (which is 4 (the valley and spin degeneration coefficients) for Si, 2 (the valley degeneration coefficients) for SiC), h is the flank constant h = 2πħ, T(E) is the transmission coefficient, fS/D (E) is the Fermi function at the Source/Drain (S/D).
The transmission coefficient is calculated from the Green’s function of equation as follows (Eq 2.6).
T (E) = Trace(ΓSGΓDG+)
The step-by-step procedure for the NEGF approach is described as follows:
Presentation of the simulation scheme
The flowchart of the computation in modeling nanodevices with the nonequilibrium Green’s function is shown in Figure 2.3 .
Figure 2.3 Flowchart of simulation involved in modeling of a nanodevice, adopted from .
– The simulation starts with the initial guess of the electrostatic potential profile (ϕ(0)(xi,yi)), which is constructed by analytical functions or from the electrostatic potential of a nearby bias point.
– The second step is to compute the contact self-energy matrices (ΣS and ΣD), which describes how the channel couples to the S/D contacts and the self-energy matrix (Σs), if Σs not zero. And then, the S/D contacts are described by a chemical potential ( s, d), which controls the carrier injection from the contacts into the channel.
– The third step is to solve the nonequilibrium Green’s function equations for the Green’s function (G) and the electron correlation function (G<). Following this, the self-energies due to electron–phonon scattering are calculated.
– Then, the electron density (diagonal elements of G<) is plugged into Poisson’s equation in order to obtain updated electrostatic potential profile. And obtained new electrostatic potential profile served as an input to solve for updated nonequilibrium Green’s functions and iterate the above process (outer left loop of Figure 2.3 until convergence is achieved.
Simulated device structure and physical parameter
The structure of the simulated SiC (or Si) NWFETs is depicted in Figure 2.4(a), The SiO2 oxide layers surrounding the Si channel are not subject to the transport calculation, but are included to compute the 3D electrostatic potential. The dimensions of the NWFETs are chosen to be close to the physical and theoretical limit (ballistic region: the sub-10nm dimensions) of MOS structures.
The device feature is gate-all-around (GAA) FET using SiC (or Si) NWs as the conduction channel. The cross section of the silicon channel is 5×5 nm2 and a gate oxide thickness (tox) of 1 nm is used as the dielectric materials (Figure 2.4(b)). We assume that there is no gate current through oxide tunneling. The source and drain extension regions are heavily n-doped (Si: ND = 1020 cm-3, SiC: ND = 2×1020 cm-3) with abrupt doping profiles. Metallic gate with the mid-gap work function (Si: 4.6 eV and SiC: 3.9 eV) is assumed. If there is no mention, the length of the channel is 20 nm, which is long enough to prevent charge penetration from the doped regions so that the effective mobility can be exactly measured.
The SiC (or Si) NWs is along the  orientation, the effective-mass approximation is assumed for the six valleys of conduction band with mt (Si: 0.191 mo, SiC: 0.25 mo) and ml (Si: 0.916 mo, SiC: 0.65 mo), where mt is the transverse effective masses, ml is the longitudinal effective masses and mo is the mass of the free electron. Other material parameters for simulation of Si and SiC are based on experimental values, as listed in Table 2.1.
Electrical transport of nanowire FET
To evaluate the device performance of (simulated or fabricated) FET, it is important to analyze some key device parameters, such as effective mobility, on/off current ratio, current density and transconductance. Among those device parameters, the mobility is one of the most important parameters that determine the performance of FET and provide useful information on the transport phenomena.
The simulation results of Kotlyar et al.  and Jin et al.  showed that the electron mobility in Si NW decreases with decreasing channel diameter. They explained this phenomenon with electron phonon wave function overlap , because an increase of electron phonon wave function overlap with decreasing channel diameter results in increased electron phonon scattering rates and consequently lower electron mobility.
On the other hand, the experimental results and simulation results of Si NWFET [8, 9] showed higher mobility in Si NWs compared to planar MOSFETs. The reduced density of electron states (DOS) for scattering in 1-D wire transport devices gives an advantage over MOSFET and thereby an enhancement in the mobility.
In case of SiC NWs, experimental results of SiC FET show lower effective mobility (below 15 cm2•V-1s-1) than that of its bulk counterpart (several hundred cm2•V-1s-1), as we discussed in the section 1.4.2. Only a few studies have reported about the electron mobility of SiC NW in the ballistic regime . In this subsection, it will be discussed the background theory of the effective mobility and simulated results of the Si and SiC NWFET.
The mobility can be extracted in the linear transport (VDS = 10 mV) regime by using the expression (Eq 2.7). = Eq 2.7 where L represents the channel length of device, G is conductance and N1D is the one-dimensional charge density along the channel.
The conductance G is evaluated according to the Landauer–Büttiker formalism as (Eq 2.8). = ℎ ∫ [− − ], Eq 2.8
where g denotes the degeneration coefficients (4 for Si, 2 for SiC), T(E) is the transmission probability at a given energy (E), s is the source chemical potential. From a theoretical point of view, a crucial point for calculation of mobility is how to correctly define the channel region to compute the charge density. The charge is not uniformly distributed over the whole channel region due to carrier penetration from the doped regions (source and drain). Therefore, a calculation of the charge density over the entire gated region gives rise to spurious results.
Figure 2.5(a) shows the effective mobility of SiC NWFET (cross sections of 5×5 nm2 and LG = 20 nm) with different gate voltage bias, which was extracted by using whole and reduced channel region integration. Here and in the following calculations, a low drain bias of VDS= 10 mV is assumed, and the temperature is fixed at T= 300 K. In case of the whole channel region, the effective mobility was drastically reduced at the low gate bias region. This can be explained by taking into account the behavior of charge penetration from the (highly doped regions) contacts, as indicated in Figure 2.5(b).
Figure 2.5 Extracted effective mobility of SiC NWFET with whole gated region extension integration (black symbol) and reduced channel region integration (red symbol), (b) reduced gate length for calculation of electron density, which prevents charge penetration from the contacts.
It is important to exclude the charge penetration from the doped regions for the estimation of the effective mobility in small devices. In experiments, the influence of doped drain and source regions can be hardly separated from the channel mobility. In case of simulation, we can simply eliminate this charge component by computing the linear charge density in a reduced region (LG – 2ΔLG, LG= 20 nm and ΔLG= 5 nm) at the center of the channel. In this way, region for the calculation of charge density is restricted over a section of the gated region characterized by an almost uniform electron distribution (as shown in Figure 2.5(b)), which is not affected by the charge penetration from the contact.
Figure 2.6 shows the effective mobility of SiC and Si NWFETs with different linear charge density (N1D). The effective mobility of SiC NWFET is smaller than that of Si NWFET. It is because the transverse effective mass of SiC NWFET is a little bit higher than that of Si NWFET (Si= 0.191 mo, SiC= 0.25 mo), which would lead to a faster decrease of the effective mobility. We observed a reduction of the effective mobility at large gate overdrive, above the threshold voltage (Vth= 0.4 V). The electron mobility decreases due to the effect of Fermi degeneracy in the ballistic case. The electron mobility of 3C-SiC and Si NWFET are 330 cm2 V-1s-1 at N1D= 9×106 cm-1 and 341 cm2 V-1s-1 at N1D= 8×106 cm-1, respectively. The calculated electron mobility⋅ of 3C-SiC and Si NWFET exhibit ⋅higher value than the experimentally obtained electron mobility of their bulk 2 V -1 s -1 at N = 3.2×10 18 -3  counterpart with the corresponding carrier concentration (3C-SiC: 200 cm cm and Si: 230 cm2 V-1s-1 at N3D= 3.6×1018 cm-3 ). The mobility enhancement⋅ mainly3Dcomes from quantum confinement and⋅the possibility of ballistic transport.
Surface roughness effect
Surface roughness (SR) scattering is main reason for mobility degradation in conventional MOSFETs at high transverse fields , because electrons are confined at the Si/SiO2 interface by an electrostatic potential well. Under high gate voltage bias, the electrostatic potential well become thinner, more electrons are confined very near the interface. Therefore, If SR scattering increases, the effective mobility decreases.
Intuitively, SR scattering is even more deleterious effect in Si NWFET than in conventional planar MOSFETS structure because the influence of the interface Si/SiO2 increases with the increase of the number of gates (multigate or gate-all-around structures). Moreover, as the device is scaled down, the ratio of the interface area to the channel volume increases. Therefore, larger fraction of carriers in the channel is significantly affected to the roughness of Si/SiO2 interface, and it might reduce the performance of Si NWFET.
SR scattering in NWs is the key scattering mechanism  as it yields a reduction of the local density of states in the channel [14, 15], as well as an increase of threshold voltage . Therefore, it seems worth critically examining SR scattering in the simulation of NWFET device.
Table of contents :
Chapter 1. Silicon carbide nanowires: growth, properties and applications
1.2 Introduction about bulk SiC
1.2.1 Polytypism in SiC
1.2.2 Properties of bulk SiC
1.2.3 Defects in SiC
1.3 SiC nanowire growth
1.3.1 Introduction: the fabrication methods of nanowires
1.3.2 Bottom-up growth mechanisms of nanowires
1.3.3 Fabrication of SiC nanowires
1.4 Properties of SiC nanowires
1.4.1 Mechanical properties of SiC nanowires
1.4.2 Electrical properties of SiC nanowires
1.4.3 Thermal property of SiC nanowires
1.5 Potential applications of SiC nanowires
1.5.1 Field emission display
1.5.2 SiC nanowires as fillers for composite matrix materials
1.5.3 NEMS applications
1.5.4 Energy conversion devices
1.5.5 Catalytic nanomaterials
1.5.6 Nanowires for self-cleaning coating films
1.5.7 Hydrogen storage
1.5.9 Bio-related application
Chapter 2. Modeling of electrical transport in Si and SiC nanowire FET
2.1.1 Self-consistent solution
2.1.2 Non equilibrium Green’s Function formalism
2.1.3 Presentation of the simulation scheme
2.2 Electrical transport of nanowires
2.2.1 Effective mobility
2.2.2 Surface roughness effect
2.3 Simulation of thermoelectric properties of Si and SiC nanowires
2.3.1 Theoretical background of thermoelectric properties
2.3.2 Simulation results of thermoelectric properties of SiC nanowires
2.3.2 Simulation results of thermoelectric properties of Si nanowires
Chapter 3. Fabrication of SiC nanostructures by top-down method
3.2 Dry etching of SiC
3.2.1 Etching mechanism of inductively coupled plasma
3.2.3 Etching phenomena
3.3 Experimental results for the fabrication of SiC nanopillars
3.3.1 Effect of metal mask species
3.3.2 Effect of SF6/O2 flow rate ratio
3.3.3 Effects of bias voltage and chamber pressure
3.3.4. Etching profile evolution over etching time
3.3.5. Hexagonal shape of SiC nanopillars
3.3.6 Dependence of polytypes and crystal orientations
3.3.7 Fabrication of SiC FinFET like structures
3.3.7 Experiments with the Bosch process
Chapter 4. SiC nanoFETs
4.1 Introduction: the state-of-the-art of nanoFET
4.1.1 Important issues for the fabrication of nanowire FETs
4.1.2 Issues for high performance of SiC nanowire FETs
4.2 Fabrication process of SiC nanowire FETs
4.2.1 Fabrication steps of SiC NWFET
4.2.2 Fabrication steps of SiC NPFET
4.3 Electrical characterization of SiC nanoFET
4.3.1 Electrical properties of SiC NWFET
4.3.1 Improvement of ohmic contact of SiC nanowire by Ni silicidation
4.3.2 Electrical property of SiC nanopillar FET
Conclusion and Perspectives