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Starting substrate: SOI
The SOI technology originates from the research on Silicon-On-Sapphire (SOS) in 1960-1970s [26], which was only applied in spaceborne and military electronics due to high cost. In 1978, K. Izumi from NTT in Japan successfully implanted oxygen below devices to form an insulating layer [27]. Since then, many methods to fabricate SOI substrates have been developed such as Separation by Implantation of Oxygen (SIMOX) [28], [29], Bond-and-Etch-Back SOI (BESOI) [30], [31], Epitaxial Layer Transfer Wafer (ELTRAN) [32] and Recrystallization of Polysilicon [33]. However, it was not until the late 1990s that a milestone fabrication process named Smart-CutTM was invented by Michel Bruel from CEA-Leti [34]. His extraordinary concept promoted the widespread application of SOI substrates in semiconductor industrials.
The SOI substrate comprises three layers: the active silicon film device layer, the buried oxide (BOX) and the silicon substrate, as shown in Figure 1.4. Transistors are integrated in the active silicon film, while the substrate serves for mechanical support [33]. Depending on the thickness of silicon film, the SOI substrates can be divided into two groups, partially-depleted (PD) and fully-depleted (FD) SOI [35], [36]: & PD SOI substrates correspond to film thickness Tsi > 2WDmax, (WDmax denotes the maximum width of the depletion region). Therefore, a neutral region subsists in the film when the transistor works in weak and strong inversion (Figure 1.4a). & FD SOI substrates correspond to film thickness Tsi < 2WDmax. This leads to the overlap of the depletion zones induced at the front-gate and back-gate interfaces. Thus, the interface potentials interact by coupling [37], as shown in Figure 1.4b.
Advantages of SOI CMOS technology
‘ PD SOI CMOS technology Compared with bulk silicon transistors, PD SOI technology has several advantages [38]–[42]: & The buried oxide simplifies the isolation of devices, and completely avoids the parasitic effects such as latch-up, charge sharing and leakage between devices [39], [40]. & Due to the natural isolation by the oxide, SOI devices are immunized from radiation effects (especially single-event effects due to charge in the channel) [38]. & SOI circuits exhibits less parasitic capacitance, substrate noise and energy consumption due to lower leakage and supply voltage [41], [42].
‘ FD SOI technology For further scaling, the ultra-thin FD SOI MOSFETs have been arousing special interest [14], [43]–[46]. Compared with PD SOI, they have additional key advantages: & Reduction of short-channel effects (SCEs): Benefiting from the ultra-thin body, the leakage paths between source and drain triggered by SCEs are suppressed, leading to limited the threshold voltage (VT) roll-off and finally to the reduction of OFF-state current and power (Figure 1.5a) [36], [47], [48]. On the other hand, drain-induced barrier lowering (DIBL) can also be reduced with the film thickness shrinking, as shown in Figure 1.5b [49]. Thinner BOX also leads to smaller DIBL due to the reduction of fringing field through the BOX and substrate [50]. In addition, the ideal subthreshold swing (~ 60 mV/dec) is achieved in ultra-thin FD MOSFETs [19]. & Multiple threshold voltage: Another attractive feature for FD SOI devices is the back-gate, which enables to adjust the threshold voltage (VT) for low power management [51], [52] (Figure 1.6). Compared with bulk silicon technology, where threshold voltage can only be tuned by process such as channel implanting and gate work function engineering, tuning VT by back-gate in FD technology is much simpler and more flexible. Wise back-gate bias also helps improving the carrier mobility [53] and SCEs [54]. & Undoped channel: An undoped channel, typical for ultra-thin FD MOSFETs, avoids the mobility degradation from channel doping and reduces the variability of the threshold voltage induced by dopants fluctuation [55]–[57].
Although ultra-thin FD SOI technology shows unrivalled advantages in suppressing short-channel effects (SCEs) and exhibits high performance, it still faces some issues, which will be explained in section 2.1.2.
Challenges of FD SOI technology
Despite compelling advantages for sub-30 nm node due to good control of electrostatic potential in the channel, FD SOI MOSFETs suffer from: increase of parasitic source/drain resistance [58]; diffusion of source/drain dopants [59]; readiness of ultra-thin SOI wafers [60], [61]; self-heating effect [62]–[65]; parasitic bipolar effect [66], [67]; coupling effects [68], [69]. In this thesis, we focus on the parasitic bipolar and coupling effects.
‘ Parasitic bipolar effect
As mentioned previously in PD SOI technology, the depletion zones do not overlap and the electric potentials of the two interfaces (gate oxide/Si film and Si film/BOX) remain independent, leading to a ‘floating’ body at the bottom of the channel [70], [71]. This floating body can trigger kink effect and parasitic bipolar action in PD SOI devices [72]. For FD SOI MOSFETs, the kink effect almost disappears (impossibility to collect majority carrier in the body that would affect the threshold voltage), but the parasitic bipolar effect still happens as long as the drain voltage is high enough [73].
Recently, Fenouillet-Beranger et al. noted a parasitic bipolar effect in ultra-thin FD SOI MOSFETS (Tsi = 10 nm) [74]. The parasitic bipolar can be triggered either by impact ionization (II) [66], [75] or by the band-to-band tunneling (BTBT) [76] around the drain region. This parasitic bipolar effect can enhance the drain leakage, as discussed in chapter 4.
The floating-body effect is not always detrimental: & Based on the transient floating-body effect, a capacitor-less single SOI transistor memory was developed [77]. & Using the BTBT, coupling and floating-body effect, Bawedin et al. proposed the Meta-Stable Dip memory cell [78]. & The Z-RAM cell was developed utilizing the parasitic bipolar effect induced by impact ionization [79].
‘ Coupling effects
The coupling effects between front- and back-gates happen when the thin SOI film is fully depleted [80], [81]. For thick body, the neutral region cuts off the link between front and back channels (Figure 1.4a). However, No such neutral region exists in ultra-thin FD SOI (Figure 1.4b), leading to interactions between front- and back-channels. The coupling effect affects the threshold voltage and mobility in the channel.
An additional coupling originates from the BOX/substrate interface. Substrate depletion is regarded as a key limiting factor, such as enhancement of DIBL, threshold voltage roll-off and parasitic back-channel conduction [82], [83]. A heavily-doped layer under the BOX, called ground plane, is adopted to suppress the substrate depletion effect [14].
Besides the PD and FD SOI substrates, there are other innovative substrates for advanced MOSFETs, which will be introduced in section 2.1.3.
Innovative materials for advanced MOSFETs
The development of the film layer transfer technology allows the conception of transistors with innovative materials, such as strained silicon [84]–[86] and Germanium-on-Insulator [87], [88], III-V materials [89], SiC [90], GaN on insulator [91]. Here, we focus on ultra-thin heavily-doped SOI wafers, three-dimensional integration and III-V compound materials.
Table of contents :
Chapter 1: General introduction
1.! Downscaling of MOSFETs
2.! State-of-the-art
2.1! Starting substrate: SOI
2.2! Advanced architecture for three-dimensional SOI transistors
3.! Objectives and organization of the thesis
Chapter 2: Characterization of heavily-doped SOI wafers by pseudo-MOSFET technique
1.! State-of-the-art for undoped SOI wafers
1.1! Experimental set-up for L-MOSFET
1.2! Measurement configuration
1.3! Parameter extraction for undoped wafers
2.! Experiments for heavily-doped (HD) SOI wafers
2.1! Sample preparation
2.2! Experimental results
2.3! Geometric factor for HD SOI wafers
2.4! Conventional Y-function for HD SOI wafers
3.! Revisited model for HD SOI wafers
3.1! Variable volume contribution
3.2! Interface accumulation
3.3! Extracted results
4.! Van der Pauw and Hall effect
4.1! Experiments set-up
4.2! Experimental results
4.3! Resistivity comparison
5.! Conclusions and perspectives
Chapter 3: Characterization of metal bonded silicon wafers
1.! State-of-the-art for characterization of metal bonded wafers
2.! Experiments set up
2.1! Sample preparation
2.2! Experimental configuration
2.3! Experimental results
3.! TCAD simulation
3.1! Employed models
3.2! Simulation results
4.! Model for estimation of bonded interface
4.1! Estimation principle
4.2! Experimental results
5.! Conclusions and perspectives
Chapter 4: Parasitic bipolar effect in ultra-thin FD SOI MOSFETs
1.! Contributions to drain leakage
1.1! Conventional drain leakage
1.2! Parasitic bipolar amplification
2.! Evidence of parasitic bipolar effect in ultra-thin FD SOI MOSFETs
2.1! Experimental results
2.2! Simulations
3.! Impact of back-gate on PBT
3.1! Experimental results
3.2! Physical mechanism of suppression of the PBT
4.! Extraction of current gain for parasitic bipolar transistor
4.1! Conventional extraction methods
4.2! Ratio of drain leakage current between short- and long-channel devices
4.3! New extraction method based on back-gate biasing
5.! Conclusions and perspectives
Chapter 5: Coupling effects in three-dimensional SOI devices
Part A: Modeling of potentials and coupling effects in inversion-mode and junctionless SOI FinFETs
1.! Coupling effects in inversion-mode vertical DG SOI FinFETs
1.1! Experiments
1.2! Analytical model
2.! Coupling effects in junctionless SOI FinFET
2.1! TCAD simulations
2.2! Modeling of 2D potential distribution in full depletion mode
Part B: Modeling of junctionless SOI FinFETs for parameters extraction
2.3! Modeling of carrier profile in partial depletion mode
2.4! Parameters extraction in accumulation mode
2.5! Conclusions on modeling of JL SOI FinFETs for parameters extraction
Part C: Application for parameters extraction in experimental GaN junctionless FinFETs
2.6! Experimental results
3.! Conclusions and perspectives
Chapter 6: General conclusions and perspectives
