Thermal Conductivity of Duralumin 𝜆dura (W/mK)

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3D Packaging with Printed Circuit Board (PCB) Technology

PCB substrates are primarily used to connect components together for 3D packaging technologies with a variety of interconnect possibilities. Usually, this PCB technology makes use of flexible or rigid PCB substrates. Besides, PCBs are very favorable for use in power conversion products as they make the manufacturing process easier.
Flex PCB substrate is usually used to realize interconnections in order to reduce the interconnect lengths formed by wire bondings. Hence to reduce the switching losses caused by stray inductances.
In addition, PCB technologies may also be used to realize 3D assemblies. Compared to 2D packaging, 3D packaging allow to create higher power density converters by using vertical interconnections and PCB embedding technology with multiple layers rather than spread out over a large surface area. For example, as shown in Fig.1-6, authors in [40] proposed a converter integrating passive components into PCB substrates to form an “embedded Passive Integrated Circuit” (emPIC). And it is demonstrated that 82% efficiency can be achieved of their 3D embedding application.
3D packaging by PCB substrates indicate the trends of power modules development in miniaturization and higher power density. However, one of the biggest challenges in using PCB technology lies in thermal problems. Since heat has further travel to reach ambient because of the additional integration layers, and insulating materials used during fabrication between layers also impedes heat dissipation.

Power Loss Measurement

It is self-evident that we need a quantitative knowledge of power loss in any power electronics system. Power loss measurement with high accuracy is important to assess system performance and optimize the characteristics of the designed systems [58]. Commonly used methods to measure power losses are sophisticated modeling, electrical methods and calorimetric methods. Their pros and cons concerning various techniques will be discussed in the following part.
 Sophisticated Modeling
Thermal component models are parameterized in terms of structural and material properties so they can be readily used to develop a library of component models for any available power module. 1) Numerical 3-Dimension (3-D) modeling Common numerical methods for thermal analysis are 3-D Finite Element Methods (FEM) and 3-D Finite Difference Methods (FDM) by 3D simulations in use of softwares such as ANSYS [59], SOLIDES-ise [60], SALOME [61], COMSOL Multiphysics [62], FloTHERM [63] etc. There are a lot of research work depending on FEM or FDM simulations to calculate the 3D thermal behaviors in power modules as in [64, 65].
For example, in [66], a simplified boundary-dependent thermal model for high power insulated-bipolar transistor IGBT modules has been developed as presented in Fig.1-14. The simulation conditions applied by the authors are heat sources (power losses) and the heatsink (cooling system). Thermal distributions are acquired in critical points and the 3D FEM simulation results could be used for accurate life-time estimation of the used IGBT module.
However, 3-D FEM or FDM simulations has limitation due to computation time in arbitrary load cycles and computer memory for fine meshes. Moreover, it may also lead to divergence in case of very high dynamic operations.

Solid Cooling

Conventional assemblies used in industrial applications based on standard modules with air cooled aluminum heat sinks are too heavy and voluminous, especially for automotive uses. Besides, the heat conduction capability of the cooling system or the thermal path of the structure is always the dominant factor of its thermal performances. So many efforts such as developing new semiconductor materials with higher thermal conductivities or improving packaging technologies, have been contributed in order to reduce the thermal resistances of the total structure with less additional components.
Recently, besides traditional solid-technologies of thermal vias, advanced thermoelectric solid-state cooling technology, based on polycrystalline miniaturized TE cooler [128], nanostructured superlattice TEC [129], mini-contact enhancement technology [130], and silicon and germanium substrate self-cooling [131] have received great attention and considerable progress has been made at the research level for high flux thermal management for microprocessors and electro-optic components. These solid-state techniques have compact structure, offer high reliability, can be locally applied, provide high cooling flux, and can be integrated with IC processing.
 Thermal Vias:
A thermal via is a plated through hole (PTH) plated with copper and is used to transfer the heat from one side of the PCB to the other side. PTH is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the structure. With thermal vias, the PCB acts as a pathway for the heat energy to reach the main heatsink, rather than serving as the heatsink itself. For example, main heat transfer path for a 2 layer PCB with thermal vias is shown in the Fig.1-28 [132].

Thermal Conductivity of Duralumin 𝜆dura (W/mK)

The two RTDs (with the corrected relationship) have been used to determine the precise thermal conductivity of duralumin 𝜆dura (W/mK). As shown in Fig.2-1, a heating resistor is mounted on the PCB substrate and a piece of glass wool for thermal insulation is applied to cover the top side of the PCB module to avoid heat convection between the heating resistor and the air. So, the dissipated power of the heating resistor will mainly pass through the duralumin column by neglecting the heat convection and heat radiation effects. Based on (1.4-11), the thermal resistance of the duralumin column between the two RTDs Rth_du could be obtained by inputting a heating power and measuring the temperature difference Δ𝜃RTD.
Measurement has been performed 5 times to obtain the average value of Rth_du. It is assumed that the ambient temperature for these measurements is constant. Relationship between temperature difference Δ𝜃RTD and input power P has been drawn in Fig.2-6. So, the thermal resistance between two RTDs is obtained as 0.187 ℃/W. Then the thermal conductivity of the duralumin 𝜆dura can be calculated by using (1.4-11). It is equal to 130.45 W/(mK). This values is postulated to be independent of temperature and kept constant to be applied for power loss calculations. The obtained value of Rth_du will be used for the power loss measurement and the deduced 𝜆dura will be applied for 3D FE simulations in the following sections.

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This part mainly focuses on the fabrication technology of PCB structure. Based on a soldering procedure of Si chip on the PCB substrate, preparation process of PCB as well as the realization of the chip attachment will be presented in order to introduce the materials and equipments used for manufacturing a PCB structure.

Preparation of PCB Substrate

A full fabrication process of PCB is shown in Fig.2-14 [161]. The typical processes to prepare the PCB substrate as shown in Fig.2-15 are described in the following five steps:
 Step 1: Creating the substrate by lamination technology with prepreg, which is a glass fabric pre-impregnated in resin. More details could be found in [161].
 Step 2: Substrate cleaning. Before covering the substrate by resin or photosensitive film, this cleaning step is important to avoid yielding a poor coating by the resin. That means, the particles or the residues left on the surface may create small holes in the deposited layer.
 Step 3: Photolithography. Firstly, coating or marking the substrate with liquid photoresist which aims to protect the copper part of the circuit. Then it is exposed to an ultraviolet radiation so that the exposed areas become soluble for positive resin. Here the etch mask with ink pattern can be created by Eagle or Altium
softwares. Lastly, the development step is realized by dipping the PCB substrate in a developer. The exposed area of the photoresist will be dissolved for the positive resin.
 Step 4: Etching. The copper etching is made directly in ferric chloride solution or with an etchant spray system. And it’s necessary to do this step repeatedly until the exposed copper part is fully cleaned.
 Step 5: Stripping. This last step is to clean the substrate with chemical reagent before the chip soldering.
More details of applied materials and fabrication technologies of PCB are described in the thesis of YU [2].

PCB Substrate with One Individual Thermal Via

Fig.3-1 depicts a typical structure of a single via. To simplify the analysis process, it is postulated that the individual via has isothermal boundary conditions on its top and bottom and adiabatic condition on its surrounding surfaces. Here, ei (mm) (i = 1,2,3) represents the thickness of each layer, and 𝜎i (W/mK) is the corresponding thermal conductivity. D (mm) stands for the via diameter. Pla (mm) is the plating thickness of thermal via. The thermal resistance of each layer Rth_i (K/W) can be obtained by (1.4-11).

PCB Substrate with Multiple Vias

After figuring out the significant via parameters according to the cases where PCB substrates have one and two thermal vias, it is much easier to analyze the common case with multiple thermal vias. As shown in Fig.3-5, via-cluster is formed by multiple vias, each individual via would function separately. In other words, all thermal vias are considered as parallel thermal resistances based on the 1D heat conduction assumption. Two typical sketches of multiple-via pattern are presented in Fig.3-6. The difference between these two patterns is related to the higher via design density allowed by pattern 2.
To simplify the analysis procedure, it is assumed that there are N (m×n: m rows, n columns) thermal vias with a pitch distance Hd between each other and these vias form a via-cluster area Lvia×Yvia (mm×mm), with via-cluster length Lvia equivalent to n×Hd and viacluster width Yvia equivalent to m×Hd. It is postulated that this multiple-via structure has isothermal boundary conditions on its top and bottom and adiabatic condition on its surrounding surfaces.

Table of contents :

Résumé en français
List of figures
List of tables
General Introduction
CHAPTER 1. State of The Art
1.1. Introduction
1.2. Power Converters
1.2.1. Semiconductor Components
1.2.2. Multilevel Converters
1.3. Power Packaging
1.3.1. Introduction
1.3.2. 2D Packaging with Direct Bonded Circuit (DBC) Technology
1.3.3. 3D Packaging with Printed Circuit Board (PCB) Technology
1.3.4. Conclusion
1.4. Thermal Analysis of Power Electronics Systems
1.4.1. Introduction
1.4.2. Thermal Measurement Methods
1.4.3. Thermal Management Solutions
1.5. Summary
CHAPTER 2. Thermal Instrumentations
2.1. Introduction
2.2. Test Bench
2.2.1. Establishment
2.2.2. RTD Sensor (PT 100) Calibration
2.2.3. Thermal Conductivity of Duralumin 𝜆dura (W/mK)
2.2.4. Temperature Measurement Equipments
2.2.5. Applied Softwares
2.3. Chip Attachment on The PCB Substrate
2.3.1. Preparation of PCB Substrate
2.3.2. Chip Soldering
2.4. Through-Hole Electroplating
2.5. Summary
CHAPTER 3. Optimization of thermal vias
3.1. Introduction
3.2. Analytical Analysis
3.2.1. PCB Substrate with One Individual Thermal Via
3.2.2. PCB Substrate with Two Thermal Vias
3.2.3. PCB Substrate with Multiple Vias
3.3. 3D FEM Analysis
3.3.1. Number of Thermal Vias N
3.3.2. Via-Cluster Surface Ratio Ro1
3.3.3. Via Diameter Ratio Ro2
3.3.4. Via Plating Thickness Ratio Ro3
3.3.5. Via Pattern
3.3.6. Copper Thickness on The PCB Substrate
3.4. Experimental Results and Discussions
3.5. Conception of The Inverse Thermal Model
3.5.1. Introduction
3.5.2. Steady State Inverse Heat Conduction Model (IHCM)
3.5.3. Dissipated Power Prediction
3.5.4. Dissipated Power and Thermal Conductivity Prediction
3.6. Summary
CHAPTER 4. Thermoelectric Cooling
4.1. Introduction
4.2. 3D FEM Analysis
4.2.1. Placement of The Peltier Device dgp and Number of Peltier Elements Np
4.2.2. Copper Thickness on The PCB Substrate
4.2.3. Modeling of The Peltier Device CP39236H
4.3. 1D Electro-Thermal Modeling
4.3.1. 1D Modeling of The Cooling Structure
4.3.2. 1D and 3D Simulation Results and Discussions
4.4. Experimental Validation
4.4.1. Test Bench
4.4.2. Results and Discussions
4.4.3. Influences of Number of Peltier Elements N
4.5. Summary
Conclusions and Perspectives
Annex A
Annex B
Annex C
Annex D


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