Transistor Level Simulation Results for the Joanneum Research Technology 

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State of the Art of Compact Models for Circuit Design with Spice Simulators

 Compact models are a set of one dimensional physical equations which describe the behaviour of a transistor in the dierent regions of operation following the classical procedure described for conventional MOSFET transistors, [3]. The idea is to describe the dependence of the drain source current equation in terms of the gate source and the drain source voltage with the least possible quantity of parameters. This is done in order to reduce the time of the simulations. The equations are thus implemented in an Spice-like simulator to obtain an electrical model with a discret device structure (resistors, capacitors, voltage and current dependent sources).
Two characteristics curves are needed to describe the DC behavior of a transistor, the transfer and the output curve. The transfer curve describe the transition of the drain source current from an O state (or leakage regime) with almost no current in the channel to a subthreshold regime with a small drain source current in the channel and then to a linear above treshold regime with a considerable high current in the channel. The output curves however, describe the transition of a transistor from a linear resistor (voltage dependent) behavior to a current source (voltage independent) behavior.
A good model, thus, would need to t in all of the above mentioned regimes, however in practice the lack of standards in the materials of the OTFTs and in the dierent parameter used to describe it, complicate the task. Several groups have reported functional models, (shown below), but the commercial simulators do not include all of them.
In order to have a compact model describing the transistor behavior, the rst is to start from the denition of the mobility as the linear parameter that describes the speed of the charges v, in a solid as directly proportional to the electric eld E applied to that solid: v = E (2.1) The electric eld E is in fact the voltage variation with the distance across the channel or dV/dx.
The current of charges traversing a unit square area with width W and thickness t, in the channel of a transistor named J is described following the classical Ohm’s law. Where is the charge per volume unity: J = v.

State of the Art of Organic Thin Film Transistors

This thesis departs from the previous works in OTFT fabrication and modeling of C. H. Kim [10] in Ecole Polytechnique, France, F. Zanella at CSEM, Switzerland and A. Petritz at Joanneum Research, Austria. A summary of the characteristics and performances of the dierents OTFTs are presented in Table 2.1 and a description of what is proposed in this thesis:
A) Ecole Polytechnique Technology: Although the operating voltages are higher, this work proposes a lower cost and easy-to-fabricate technology by shadowmasks of OTFTs and the design of several analog blocks. A spice model present in a commercial simulator would be adjusted. A mismatch model will be presented and a statistical description of the variations in the extracted parameters will be described.
B) Joanneum Research Technology: This thesis work presents an adaptation of the OTFT technology fabricated by shadow masks from the work of A. Petritz, to a contact photolithographic technology. Two analysis are presented: rst, large width OTFTs (ideal for analog design) will be tested in order to be aware of gate leakage. And second, the source drain interface will be improved by the reduction in the injection barrier. The contact resistances was thus calculated and then the OTFT was modeled with the same adapted a-Si Spice model explained in this chapter.
The model tting presented by Zanella will be improved by this more developped model. This works targets also the reduction in its operating voltages, compared to his publication.

Ampliers on Flexible Foils

This thesis works aims to improve the state of the art of ampliers on exible foils. In this eld, several groups have been in a race to obtain the best performance on gain and bandwidth. Their peek performances are complementary, for example Maiellaro et al. [14] has shown the highest DC gain reported to date, but its bandwith is rather slow of several Hz, with a high power consumption using a 50 V supply voltage. On the contrary Marien et al. at IMEC [15] has shown a more complex amplier with 3 stages using a lower power consumption but a larger bandwidth with several tenths of Hz. The fact that the mobility in the organic material is still poor and that the dielectric is thick, do not allow to have a high transconductance OTFT which is key in the design of ampliers. Moreover, the bandwidth are rather short because the channel lengths are longer till several microns.

CAD Tools for Emerging Technologies

Computed Aided Design (CAD) tools are common for CMOS design and other industrial technologies.
Adapted CAD tools for emerging technologies are rare as well, mainly due to the lack of the commercialization of the applications. According to the authors knowledge, Vila [25] at Universidad Autonoma de Barcelona is the only one who worked in CAD tools for printed electronics. In this thesis, a full CAD system of tools from LIP6-UPMC, is presented as a proof of concept including as well placement and routing tools (not presented in Vila’s CAD system). This work, is thus a rst approach to incorporate also in the future, the full physical model developed in LPICM-Ecole Polytechnique.

Energy management for exible devices

In this eld several interesting applications have been presented. Energy production and harvesting is a key concept in todays electronic industry and there are promising approaches also for the exible electronic world. One of the most remarkable applications from a practical point of view was the ultra exible solar cell presented by Kaltenbrunner et al. [33] shown from a to e in Fig. 2.9 with a 10 W/g of specic weight higher than the 3W/g of a conventional CIGS cell, showing one of the highest eciency per weight presented to date. The group of Someya showed wireless power transmitters, [34] using again its active matrix of OTFTs for addressing rows and columns,  where a large area sheet of coils and MEMS was superposed and then it transfered energy to a group of LEDs at a short distance as presented in F of Fig. 2.9. The group of Prof. Bauer showed also exible and stretchable batteries [35] with a 6,5 mA h and a 25% strain after 700 mechanical  stretch cycles, presented in G. The group of Someya also showed an energy harvesters with an insole pedometer in [36], using a PVDF piezoelectric sheet and the same concept of the active matrix already shown in other projects.

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e-Health applications with exible and biocompatible materials

The last frontier in this eld is to deliver signal treatment directly into our bodies to communicate with sensors in the outside to recover critical life signals and in chirurgical procedures. The group of John Rogers at the University of Illinois at Urbana-Champaign is one of the leaders in this eld showing applications with biocompatible materials already implanted in the body of animals. As shown in Fig. 2.11, in A) an electroencephalogram for in Vivo brain signals sensing was tested on a rat in [38]. Another group who has succesfully tested implantable neural probes with OECTs is the Malliaras group, as presented in [39] with one of the highest transconductance transistors reported to date which enables higher SNR recovery of signals from the brain. Continuing in the  gure in B) catheters with ablation properties for surgical procedures were succesfully tested in a rabbit heart in [40]. In C) several surgical devices were fabricated with sensors to be placed on the ngers in order to enhance the capabilites of a surgeon, presented in [41]. In D) and E) other epidermal sensors are presented in [42], where a set of coils, chemical and pressure sensors are implemented as an articial skin or tattoos as a way to reconver important health information and send them to other conventional electronic devices which will analyze it.

Layout Design Automation Tools

With a collaboration at LIP6-UPMC, this thesis work contributed to the elaboration of a design tool kit for the LPICM-Ecole Polytechnique Technology. A system of open source VLSI CAD tools (Alliance ©) was customized for the layout design and automation. A proof of concept was elaborated for the layout of a sigma delta modulator. Several place and route tools were implemented as well, for every cell in a predened template of a shadow mask in order to design a layout and for technology migration from node to node. These customized tools could be extended for any other thin lm transistors technology. This work is published in [45].

Table of contents :

List of Figures
List of Tables
Part I Introduction to Electronics with Organics and Flexible Materials
1 Introduction
1.1 Introduction
1.2 Outline
2 Problem Denition and Motivation
2.1 Introduction
2.1.1 Technology Process
2.2 State of the Art of Compact Models for Circuit Design with Spice Simulators
2.3 State of the Art of Organic Thin Film Transistors
2.4 State of the Art of Circuits
2.4.1 Ampliers on Flexible Foils
2.4.2 Comparators
2.4.3 Analog to Digital Converters
2.4.4 CAD Tools for Emerging Technologies
2.5 State of the Art of Applications
2.5.1 Signal Treatment Systems
2.5.2 Pressure Sensors
2.5.3 Flexible Displays
2.5.4 RFID Tags
2.5.5 Energy management for exible devices
2.5.6 Smart Textiles
2.5.7 e-Health applications with exible and biocompatible materials
2.6 Major Contributions
2.6.1 Technology Process
2.6.2 Circuit Design
2.6.3 Layout Design Automation Tools
2.7 Conclusion
Part II Technology Process
3 CONFIDENTIAL: Systematic Parameter Characterization & Mismatch Model for Analog Design
3.1 Introduction
3.2 Mismatch Model Development
3.3 Manufacturing Technology Process
3.3.1 Engineering the Polymeric Gate Dielectric
3.3.2 Engineering the Semiconductor Pentacene Layer
3.3.3 Source and Drain Metal Deposition and Contact Resistance Calculation
3.4 Electrical & Mismatch Characterization
3.4.1 Characteristics I-V Curves, Mobility and Ageing Eects
3.4.2 Modeling and Mismatch of Extracted Parameters in OTFTs
3.5 Conclusion
4 CONFIDENTIAL: Low Power OTFT by Photolithography and Self-Alignment Process
4.1 Introduction
4.1.1 Frequency Behavior of Transistors
4.2 Manufacturing Technology Process
4.2.1 Photolithography and Self Alignment Process Technology
4.2.2 Issues and Diculties of Manufacturing Structures by Photolithography .
4.2.3 Engineering the Polymeric Gate Dielectric
4.2.4 Engineering the Semiconductor Pentacene Layer
4.3 Electrical Characterization
4.3.1 Gate Leakage Current Voltage Curves
4.3.2 Engineering the Source and Drain Contact Resistance
4.3.3 Extraction of Parameters and Modeling of OTFTs
4.4 Conclusion
Part III Circuit Design
5 CONFIDENTIAL: Design of Functional Analog Circuits with Few Organic Transistors
5.1 Introduction
5.2 Gain Equations of a Diode Load Amplier
5.2.1 Sizing OTFTs
5.3 6 OTFT Fully Dierential Voltage Amplier
5.3.1 Simulation Results for the Orgatech Technology
5.3.2 Simulation Results for the Joanneum Research Technology
5.3.3 Comparison of Performances of Both Technologies
5.4 9 OTFT Source Coupled Latch Comparator
5.4.1 Simulation Results for the Orgatech Technology
5.4.2 Simulation Results for the Joanneum Research Technology
5.4.3 Comparison of Performances of Both Technologies
5.5 25 OTFT, 1-Bit 1st Order Sigma Delta Modulator
5.5.1 System Level Modeling
5.5.2 Transistor Level Simulation Results for the Orgatech Technology
5.5.3 Transistor Level Simulation Results for the Joanneum Research Technology
5.5.4 Comparison of Performances of Both Technologies
5.6 A Discussion on Yield with Monte Carlo Simulations
5.6.1 Monte Carlo Simulations for the Dierential Amplier
5.7 Conclusion
6 CONFIDENTIAL: Implementation of Analog & Digital Circuits on Plastic .
6.1 Introduction
6.2 Testing Plastic Circuits
6.3 Characterization of Moderate Gain-Fast Inverters and Logic Gates
6.4 Characterization of Analog Circuits
6.4.1 Moderate Gain-Fast Dierential Voltage Amplier
6.4.2 Fast Source Coupled Latch Comparator
6.5 Discussion of the Results
6.6 Conclusion
7 Open Source CAD Layout Tools for Thin Film Emerging Technologies
7.1 Introduction to Alliance CAD Tools
7.2 Alliance Concept for Emerging Printed and Flexible Technologies
7.3 Proof of Concept for a Layout of Integrated Circuits with Organic TFTs
7.3.1 Graal environment for symbolic layout design
7.3.2 Design Rules for Organic Thin Film Transistor Technology
7.3.3 Dierential Amplier Layout
7.3.4 Comparator Layout
7.3.5 Sigma Delta Modulator Layout
7.4 Conclusion
Part IV Conclusions
8 Conclusion and FutureWork
8.1 Research Overview.
8.1.1 Design Kit with Organic Transistors
8.1.2 Circuit Design of Functional Analog and Digital Circuits on Plastic Foils
8.1.3 Customization of the Alliance CAD Systems for Emerging TFT Technologies
8.2 Future Work
9 List of Publications
Appendix A
A.1 Analog to Digital Converters Principal Relations
A.1.1 Conventional Oversampled Analog to Digital Converters Signal to Noise Ratio Relation
A.1.2 Analog to Digital Converters based on Sigma Delta Modulators Signal to Noise Ratio Relation
Appendix B
B.1 Alliance CAD Tools in CMOS Design


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