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Table of contents
1 Introduction
1.1 State of the art in transistor industry
1.1.1 Limits of scaling
1.1.2 Heterogeneous Scaling and Technology Boosters
1.1.3 Possible Solutions in the Roadmap
1.2 III-V MOSFETs
1.2.1 Motivation for ACM/Why III-V?
1.2.2 ACM Trade-offs
1.2.3 Current Status of ACM Devices
1.3 Need to evaluate SCEs in III-V MOSFETs
1.4 Aim of the Thesis
1.5 Organization of the Thesis
2 Modeling of the channel potential in a MOSFET
2.1 Introduction
2.2 Channel Potential Modeling
2.2.1 Analytical Modeling
2.2.2 Concept of the extra potential in a short channel MOSFET
2.2.3 FlexPDE Numerical Simulation
2.2.4 Comparison: Model Vs Numerical Simulation
2.3 The Question of Boundary Conditions
2.3.1 Impact of the Source/Drain regions on SCEs
2.3.2 Electrostatics: Variation of the minimum of channel potential (top of the barrier)
2.4 Effective Built-In Potential, V effbi
2.4.1 Analytical Modeling of V effbi
2.5 Impact of the Source/Drain doping
2.6 Corrected Short Channel Effects
2.7 Conclusion
3 Origin of SCE increase in III-V MOSFETs
3.1 SCEs in III-V MOSFETs
3.2 Quantum Effects and SCEs in Subthreshold Regime
3.2.1 Concept of Dark Space
3.2.2 Simulation Methodology
3.2.3 Simulation Results
3.3 Impact of Material Parameters
3.4 DIBL in Strong Inversion Regime
3.4.1 Effective current and DIBL
3.4.2 Dark space and DIBL in strong inversion
3.4.3 Definition and extraction method of the DIBL in strong inversion regime
3.4.4 Impact of quantum effects and dark space on the DIBL in inversion
3.5 Impact of the architecture on the SCEs
3.5.1 Impact of barrier layers: QWFET Vs thin films
4 Source to Drain Tunneling and III-V MOSFETs
4.1 Leakages in Nanoscale MOSFETs
4.2 Source to Drain Tunneling
4.2.1 The WKB approximation
4.2.2 Effective barrier size modulation
4.3 Source Drain Tunneling and ACM
4.4 Quantum Confinement and SDT
4.5 Conclusions
5 Conclusions and Future Perspectives
5.1 Conclusions
5.2 Future Perspectives
