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Table of contents
General Introduction
Outline and aim of the thesis
Millimeter Wave Device Measurement and Characterization in Silicon Integrated Circuits
1.1 State of the Art and Problem Description
1.1.1 Transmission Lines for Millimeter-Wave and Sub-Millimeter-Wave Frequencies and Applications
1.1.2 Slow-Wave Coplanar Waveguide (S-CPW) Transmission Line
1.1.3 Motivation: Applications at Millimeter-Wave Frequencies and Above
1.1.4 Electromagnetic Modeling and Measurement Uncertainties
1.1.5 De-embedding and Challenges
1.1.6 De-embedding with and without Interconnect/Accesslines
1.1.7 Bended-Accessline De-embedding
1.1.8 Excessive Losses at Millimeter Wave Frequencies and Above
1.1.9 Other Measurement Challenges
1.1.10 Conclusion of State of the Art and Problem Description
1.2 On-Wafer Measurement and Challenges at Millimeter Wave Frequencies
1.2.1 Calibration and Challenges
1.2.2 RF Probes
1.3 Conclusion
1.4 References
De-embedding Methods
2.1 Classification of De-embedding Methods
2.1.1 Lumped Equivalent Circuit Model
2.1.2 Cascaded Matrix Based Models
2.1.3 Cascaded Matrix with Lumped Equivalent Models
2.1.4 Conclusion and Further studies of Classification of De-embedding Methods
2.2 BiCMOS 55 nm Silicon Technology
2.3 Proof of Concept with ADS
2.3.1 Pad-Acceslines Parasitics Models
2.3.2 De-embedding Structures: Known Parasitics De-embedding
2.3.3 Analysis of Lumped Equivalent Circuit Model De-embedding Methods
2.3.4 Analysis of Cascaded Matrix Based Model De-embedding Methods
2.3.5 Analysis of Hernandez Method
2.3.6 Analysis of Cascaded Matrix with Lumped Equivalent Model De-embedding Methods
2.3.7 Conclusion of Proof of Concept with ADS
2.4 Proof of Concept with HFSS
2.4.1 Parasitics Model: Unknown Parasitics De-embedding
2.4.2 De-embedding Structures
2.4.3 Benchmarking and Comparison of De-embedding Methods
2.5 Conclusion
2.6 References
Half-Thru De-embedding
3.1 Half-Thru De-embedding
3.2 Theoretical Analysis
3.3 Proof of Concept with Known Electrical Model Parasitics
3.3.1 Simulation and De-embedding Results with Known Parasitics using ADS
3.3.2 Conclusion of Proof of Concept with ADS
3.4 Proof of Concept with Unknown EM Model Parasitics
3.4.1 Measurement Setup and De-embedding Structures
3.4.2 Simulation and Results: Benchmarking and Comparison with TRL
3.4.3 Simulation with and without accessline
3.4.4 Effect of the Load Value Analysis
3.4.5 Comparison with Effect of the Characteristic Impedance of the Line of the TRL
3.4.6 Conclusion of Proof of Concept with HFSS
3.5 Extraction of the Load value for Half-Thru De-embedding
3.5.1 Open De-embedding
3.5.2 Open-Short De-embedding
3.5.3 Load value extraction with Kolding’s Method
3.5.4 Simulation and Results of Load Extraction Methods
3.5.5 Half-Thru De-embedding with Different Load Extraction Methods
3.5.6 Conclusion of Extraction of Load Value for Half-Thru De-embedding
3.6 Simplified Half-Thru De-embedding: Thru-Load De-embedding
3.6.1 Simulation and Comparison with Half-Thru De-embedding
3.7 Conclusion
3.8 References
Measurements and Electromagnetic Modeling Analysis of De-embedding Methods
4.1 AMS 0.35 μm CMOS Technology
4.2 Fabrication Map
4.3 Comparison of Half-Thru De-embedding and TRL
4.3.2 Load value Extraction
4.3.3 Comparison of Half-Thru De-embedding and TRL
4.3.4 Analysis of Excessive loss in S-CPW of 65 Ω and 30 Ω
4.3.5 Impact of EM-Model in De-embedding
4.3.6 De-embedding: CPW Transmission Line as DUT
4.3.7 Conclusion of Comparison of Half-Thru De-embedding and TRL
4.4 EM-Model Issues and Analysis
4.4.1 On-wafer: Fabricated Transmission Lines
4.4.2 EM – Model of Measured CPW transmission line
4.4.3 EM – Model of Measured CPW transmission line with adjacent cells
4.4.4 EM – Model of Millimeter Wave Probe
4.4.5 EM – Model of measured CPW transmission line with Millimeter Wave Probe Model and Adjacent Cells
4.4.6 De-embedding with the realistic EM- Model
4.4.7 Reasons of Excessive Loss
4.4.8 Other Possible Losses
4.4.9 Conclusion of EM-Model Issues and Analysis
4.5 Solutions
4.5.1 Conclusion of On-wafer Measurement Issues and Possible Solutions
4.6 Half-Thru De-embedding and Thru-Load De-embedding Analysis
4.6.1 De-embedding with Different Length of the DUT
4.6.2 De-embedding with Different Characteristic Impedance of DUT
4.6.3 Half-Thru De-embedding with Different Load Extraction Methods and with Different Load Values
4.6.4 De-embedding with Different Accessline Topology
4.6.5 Comparison and Benchmarking of de-embedding methods
4.6.6 De-embedding with Bended-Accessline Model
4.6.7 Conclusion of Half-Thru De-embedding and Thru-Load De-embedding Analysis
4.7 Half-Thru de-embedding and Thru-Load de-embedding in B55 nm Technology
4.8 Conclusion
4.9 References
Conclusion and Perspective
Perspectives
References
