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Table of contents
Abbreviations
1.1 A brief historical review of CMOS technology
1.2 3D integration technologies overview
1.3 Electrical measurement and analysis methods
1.4 Challenges & Motivation
1.5 State-of-the-art studies on electromagnetic coupling in 3D technologies
1.6 Main contributions and thesis outline
2.1 The MOSFET transistor
2.1.1 Metal-Oxide-Semiconductor Capacitor operation regimes
2.1.2 Definition of MOSFET electrical parameters
2.1.3 Body effect
2.1.4 Short-channel effects
2.2 The FD-SOI device architecture
2.2.1 SOI substrate technology
2.2.2 FDSOI device geometry
2.2.3 Front/Back interface charge coupling
2.3 Electromagnetic coupling and transfer of energy between electrical components
2.4 Noise sources in devices and circuits
2.4.1 Intrinsic noise sources
2.4.2 Extrinsic noise sources
2.4.3 Noise coupling in circuits
2.5 Conclusion
3.1 3D sequential structure description
3.1.1 Mixed-signal opportunities by the use of 3DSI
3.1.2 3DSI process flow for digital devices
3.1.3 Characteristic dimensions and performance of 3DSI devices under test
3.1.4 Structure layout of 3DSI devices under test
3.2 Impact of DC coupling on top/bottom device performance
3.2.1 Experimental results
3.2.2 Simulation results
3.2.3 Impact of static coupling on the performance of top-tier digital devices (VDD=1V)
3.2.4 Impact of static coupling on the performance of top-tier analog devices (VDD=2.5V)
3.3 Impact of AC coupling on top/bottom device performance
3.3.1 Small-signal analysis
3.3.2 Transient response of top-tier devices to bottom-tier device aggressor signals
3.3.3 Inter-tier versus intra-tier coupling
3.4 Conclusion
4.1 Impact of inter-tier coupling on circuit operation
4.1.1 2-bitcell Sequential 3D SRAM (Digital on Digital case)
4.1.2 RO stacked on top of an analog tier (Mixed-Signal/RF on Analog case)
4.1.3 RO stacked on top of a digital tier (Mixed-Signal/RF on Digital case)
4.2 Methods and techniques to mitigate inter-tier coupling effects in 3DSI
4.2.1 Critical dimensioning of 3DSI structures and 3D design rules
4.2.2 Inter-tier shielding through GP: challenges and solutions
4.3 Conclusion
5.1 Introduction
5.2 Principles and operation of a CMOS imager
5.2.1 CIS standard architectures
5.2.2 Pixel metrics
5.2.3 Pixel noise parameters
5.2.4 Process integration optimization
5.3 Inter-tier Coupling at Device Level
5.3.1 Simulation Setup
5.3.2 Impact on electrical parameters
5.4 Inter-tier Coupling at Pixel Level
5.4.1 Read-out circuit block and pixel metrics
5.4.2 Impact of TG coupling on pixel electrical parameters
5.4.3 Inter-tier GP necessity
5.5 Conclusion
6.1 Parasitic extraction of lumped coupling elements in 3DSI
6.1.1 Definition of coupling capacitances in 3DSI
6.1.2 Effect of 3D contacts on coupling capacitances
6.2 Coupling-induced VTH shift modeling for stacked devices
6.2.1 Charge-coupling factor expression for long-channel top-tier devices
6.1.1 Modeling the effective ILD capacitance of stacked devices (CILD,eff)
6.3 Inter-tier dynamic coupling effects modeling
6.4 Inter-tier GP shielding modeling
6.4.1 DC modeling of inter-tier GP – Impact on coupling induced ΔVTH of the stacked devices
6.4.2 AC modeling of inter-tier GP
6.5 Conclusion
BIBLIOGRAPHY
