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Table of contents
Chapter 1: General introduction
1.! Downscaling of MOSFETs
2.! State-of-the-art
2.1! Starting substrate: SOI
2.2! Advanced architecture for three-dimensional SOI transistors
3.! Objectives and organization of the thesis
Chapter 2: Characterization of heavily-doped SOI wafers by pseudo-MOSFET technique
1.! State-of-the-art for undoped SOI wafers
1.1! Experimental set-up for L-MOSFET
1.2! Measurement configuration
1.3! Parameter extraction for undoped wafers
2.! Experiments for heavily-doped (HD) SOI wafers
2.1! Sample preparation
2.2! Experimental results
2.3! Geometric factor for HD SOI wafers
2.4! Conventional Y-function for HD SOI wafers
3.! Revisited model for HD SOI wafers
3.1! Variable volume contribution
3.2! Interface accumulation
3.3! Extracted results
4.! Van der Pauw and Hall effect
4.1! Experiments set-up
4.2! Experimental results
4.3! Resistivity comparison
5.! Conclusions and perspectives
Chapter 3: Characterization of metal bonded silicon wafers
1.! State-of-the-art for characterization of metal bonded wafers
2.! Experiments set up
2.1! Sample preparation
2.2! Experimental configuration
2.3! Experimental results
3.! TCAD simulation
3.1! Employed models
3.2! Simulation results
4.! Model for estimation of bonded interface
4.1! Estimation principle
4.2! Experimental results
5.! Conclusions and perspectives
Chapter 4: Parasitic bipolar effect in ultra-thin FD SOI MOSFETs
1.! Contributions to drain leakage
1.1! Conventional drain leakage
1.2! Parasitic bipolar amplification
2.! Evidence of parasitic bipolar effect in ultra-thin FD SOI MOSFETs
2.1! Experimental results
2.2! Simulations
3.! Impact of back-gate on PBT
3.1! Experimental results
3.2! Physical mechanism of suppression of the PBT
4.! Extraction of current gain for parasitic bipolar transistor
4.1! Conventional extraction methods
4.2! Ratio of drain leakage current between short- and long-channel devices
4.3! New extraction method based on back-gate biasing
5.! Conclusions and perspectives
Chapter 5: Coupling effects in three-dimensional SOI devices
Part A: Modeling of potentials and coupling effects in inversion-mode and junctionless SOI FinFETs
1.! Coupling effects in inversion-mode vertical DG SOI FinFETs
1.1! Experiments
1.2! Analytical model
2.! Coupling effects in junctionless SOI FinFET
2.1! TCAD simulations
2.2! Modeling of 2D potential distribution in full depletion mode
Part B: Modeling of junctionless SOI FinFETs for parameters extraction
2.3! Modeling of carrier profile in partial depletion mode
2.4! Parameters extraction in accumulation mode
2.5! Conclusions on modeling of JL SOI FinFETs for parameters extraction
Part C: Application for parameters extraction in experimental GaN junctionless FinFETs
2.6! Experimental results
3.! Conclusions and perspectives
Chapter 6: General conclusions and perspectives
