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Table of contents
1 Introduction
2 Non-volatile semiconductor memories
2.1 Types of semiconductor memories
2.1.1 Market trends
2.1.2 Classification
2.1.2.1 Stand-alone and embedded memories
2.1.2.2 Memory performance
2.1.2.3 Memory architecture: random access
2.1.2.4 Read-Only Memory (ROM)
2.1.2.5 Flash Memory
2.1.2.6 Emerging memories
2.1.3 Comparison
2.2 One-Time Programmable memories
2.2.1 OTP in semiconductor markets
2.2.2 Historical background
2.2.2.1 The storage matrix
2.2.2.2 Laser fuse
2.2.3 eFuse memories
2.2.3.1 eFuse technologies
2.2.3.2 eFuse macros
2.3 Antifuse memories
2.3.1 Programming mechanism
2.3.2 Bitcell architecture
2.3.2.1 Drift antifuse bitcell
2.3.2.2 Cascode antifuse bitcell
2.3.2.3 Dual-port cascode bitcell
2.3.2.4 Multi Antifuse cascode bitell
2.3.3 Antifuse macros
2.4 eFuse versus Antifuse
2.5 Conclusion
3 Antifuse memories and gate-oxide breakdown
3.1 Modeling approach
3.2 Gate-oxide breakdown mechanisms
3.2.1 Current transport processes in dielectrics
3.2.1.1 Fowler-Nordheim tunneling current
3.2.1.2 Direct tunneling current
3.2.1.3 Frenkel-Poole transport
3.2.2 Statistical approach
3.2.2.1 Weibull distribution
3.2.2.2 Practical statistical study on antifuse bitcells
3.2.2.3 Percolation model
3.2.3 Voltage acceleration of time-to-breakdown
3.2.3.1 Empirical approach
3.2.4 Physics-based models
3.2.4.1 Anode Hole Injection: 1/E model
3.2.4.2 Thermo-Chemical: E model
3.2.4.3 Hydrogen release
3.2.5 Conclusion and perspective for antifuse bitcells
3.3 Antifuse bitcells and high-K dielectrics
3.3.1 High-K dielectric breakdown
3.3.2 Perspectives
3.4 Time-to-Breakdown characterization
3.4.1 Gate-oxide breakdown event
3.4.1.1 Breakdown modes
3.4.1.2 Focus on soft and progressive breakdown modes .
3.4.2 Antifuse bitcell characterization methods
3.4.2.1 DC voltage ramp
3.4.2.2 Successive high voltage pulses
3.4.2.3 Current measurements using a series resistor
3.4.2.4 Transmission Line Pulse
3.4.2.5 Fast current measurements using a RF bias-Tee
3.4.3 Conclusion and perspectives
3.5 Conclusion
4 TDDB modeling for antifuse bitcell design
4.1 Methodology
4.1.1 Typical Time-to-Breakdown measurements
4.1.2 Wearout current and voltage operating point
4.2 Wearout current modeling
4.2.1 Fowler-Nordheim tunneling
4.2.1.1 Analytical expression
4.2.1.2 Practical example
4.2.2 Conclusion
4.3 Time-to-breakdown modeling
4.3.1 Measurements and distributions
4.3.2 Identification of the voltage-acceleration law
4.3.3 RF measurements
4.3.4 Conclusion
4.4 Optimization of the antifuse bitcell design
4.4.1 Modeling approach
4.4.1.1 Antifuse bitcell equivalent circuit
4.4.1.2 Expression of Vcap
4.4.1.3 Model output
4.4.2 Application and verification
4.4.2.1 Antifuse bitcell dimensions
4.4.2.2 Identification of parameters
4.4.2.3 Results
4.4.2.4 Focus on the operating point
4.4.3 Method of optimization
4.4.3.1 Methodology and algorithm
4.4.3.2 Results
4.4.4 Conclusion
4.5 Cascode antifuse bitcell
4.5.1 Architecture and performance
4.5.2 High-K cascode antifuse bitcell
4.5.2.1 Wearout current measurements
4.5.2.2 Time-to-breakdown measurements
4.5.2.3 Discussion
4.6 Conclusion
5 Side effect: Bulk current overshoot
5.1 Facts
5.1.1 Antifuse devices
5.1.1.1 Single drift
5.1.1.2 Single capacitor
5.1.1.3 Conclusion
5.2 Characterizations of the phenomenon
5.2.1 DC characterizations
5.2.2 Impact of programming conditions
5.2.2.1 Programming voltage
5.2.2.2 Cumulative programming
5.2.2.3 Programming current
5.2.2.4 Summary & conclusion
5.3 Analysis of assumptions on the root cause
5.3.1 Electron and hole transport
5.3.1.1 Wearout phase
5.3.1.2 Post-breakdown phase
5.3.2 Parasitic bipolar transistor
5.3.2.1 Current signs and polarities
5.3.2.2 P-N-P structure
5.3.2.3 Current-gain simulations
5.4 Summary and conclusion
6 Post-breakdown phase and read current
6.1 Read operation basics
6.1.1 Read current distributions
6.1.2 Breakdown path characteristic
6.1.3 Perspectives
6.2 Impact of the post-breakdown conditions
6.2.1 Post-breakdown current limiter circuit
6.2.1.1 Topology and design
6.2.1.2 Performance
6.2.2 Read current distributions & characteristics
6.2.2.1 Read current distributions
6.2.2.2 Breakdown path characteristic
6.2.2.3 Cascode bitcell
6.2.3 Discussion
6.3 Conclusion
7 32-nm CMOS Advanced antifuse memory demonstrator
7.1 Key features and operating modes
7.1.1 Functionalities
7.1.1.1 Standard programming mode
7.1.1.2 Advanced programming mode
7.1.1.3 Read mode
7.1.2 Specifications
7.2 Programming current limiter
7.2.1 Topology and design
7.2.2 Simulations
7.2.3 Implemented solutions
7.2.4 Conclusion
7.3 Programming detection system
7.3.1 Configurable bitline multiplexer
7.3.2 Programming current sensor
7.3.3 Post-breakdown time delay
7.4 Conclusion
8 Conclusion
References
