The AES algorithm

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Table of contents

1 Introduction 
1.1 Security and insecurity
1.1.1 From Herodotus to cryptographic processors
1.1.2 The Evaluation Assurance Level
1.2 From the Smart-Cards to the secure products
1.2.1 Smart Cards
1.2.2 A secure Environment
1.2.3 The Smart Cards market trend
1.2.4 Smart Card Readers
1.3 Side channel attacks
1.3.1 Timing analysis
1.3.2 Power dissipation analysis: SPA, DPA
1.3.3 Electromagnetic analysis
1.3.4 Acoustic analysis
1.4 Conclusions
2 Three cryptographic algorithms 
2.1 The AES algorithm
2.2 The DES algorithm
2.3 The SHA
2.4 Conclusions
3 Hardware and software implementations of cryptographic algorithms: state of the art 
3.1 General Purpose Processors
3.1.1 The NEC DRP
3.1.2 The Crow FPGA Implementation
3.1.3 The Zippy Project
3.2 Hardwired macros
3.2.1 The Sharma macro
3.2.2 The G-Plus AES implementation
3.2.3 The Trichina Coprocessor
3.2.4 The Eli Biham DES implementation
3.2.5 The Saqib implementation of DES
3.2.6 The Ahmad hardware implementation of SHA
3.2.7 The Chavez hardware implementations of SHA
3.2.8 The Cadence Hashing Algorithm Generator SHA-256
3.3 Conclusions
4 Proposing a recongurable cryptographic coprocessor: Celator 
4.1 The system: CPU, Memory, peripherals, bus
4.2 Celator hardware architecture
4.2.1 The Processing Element Array
4.2.2 The Processing Element { Condential
4.2.3 The Controller { Condential
4.2.4 CRAM
4.2.5 The Interface unit
4.3 Considerations about Celator hardware architecture
5 Validating Celator on FPGA 
5.1 AES
5.1.1 Implementation of the AES into a PE Array { Condential
5.1.2 FPGA results
5.1.3 ASIC results
5.2 DES
5.2.1 Implementation of the DES into a PE Array { Condential
5.2.2 FPGA results
5.2.3 ASIC results
5.3 SHA
5.3.1 Implementation of the SHA into a PE Array { Condential
5.3.2 FPGA results
5.3.3 ASIC results
6 Conclusions and Further Work 
7 Resume en langue francaise de la these intitulee « Design and development of a recongurable cryptographic co-processor » par Daniele Fronte 
7.1 Resume
7.2 Introduction
7.3 Trois algorithmes cryptographiques
7.3.1 L’algorithme AES
7.3.2 L’algorithme DES
7.3.3 L’algorithme SHA
7.4 Implementations materielles et logicielles d’algorithmes cryptographiques : etat de l’art
7.4.1 Le NEC DRP
7.4.2 La macro SHARMA
7.5 L’architecture materielle de Celator
7.5.1 Le reseau de PE
7.5.2 Le Sequenceur
7.5.3 La CRAM
7.6 Comment Celator execute les algorithmes cryptographiques
7.6.1 Les transformations d’AES
7.6.2 Les transformations de DES
7.6.3 Les transformations de SHA-256
7.6.4 Modes ECB et CBC
7.7 Resultats et discussions
7.8 Conclusions