Hardware Transactional Memory

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Table of contents

INTRODUCTION
THESIS OUTLINE
1 CHAPTER 1: PROBLEM DEFINITION
1.1 PROBLEM FOCUS
1.2 AIMS AND OBJECTIVES
1.3 RESEARCH QUESTIONS
2 CHAPTER 2: BACKGROUND
2.1 SINGLE CHIP PARALLEL COMPUTERS
2.2 DATABASE SYSTEMS AND TRANSACTIONS
2.3 TRANSACTIONS VS. LOCKS
2.4 TRANSACTIONAL MEMORY
2.4.1 Hardware Transactional Memory
2.4.2 Software Transactional Memory
2.4.3 Hybrid Transactional Memory
2.5 STM DESIGN ALTERNATIVES
2.5.1 Transaction Granularity
2.5.2 Update Policy
2.5.3 Write Policy
2.5.4 Acquire Policy
2.5.5 Read Policy
2.5.6 Conflict Detection
2.5.7 Concurrency Control
2.5.8 Memory Management
2.5.9 Contention Management
3 CHAPTER 3: METHODOLOGY
3.1 QUALITATIVE RESEARCH METHODOLOGY
3.1.1 Literature Review
3.1.2 Background Study
3.1.3 Selection and Suitability of STM systems
3.1.4 Selection and Suitability of Benchmarks
3.2 QUANTITATIVE RESEARCH METHODOLOGY
3.2.1 Selection and Suitability of STM Performance Metrics
3.2.2 Experimentation
3.2.3 Analysis of Gathered Results
4 CHAPTER 4: THEORETICAL WORK
4.1 RSTM
4.1.1 RSTM Overview
4.1.2 Design Features
4.1.3 Implementation
4.2 TL2
4.2.1 TL2 Overview
4.2.2 Global Version Clock
4.2.3 TL2 – Algorithm
4.2.4 TL2 – Variants
4.3 TINYSTM
4.3.1 TinySTM Overview
4.3.2 TinySTM – Algorithm
4.3.3 Implementation
4.3.4 Hierarchical Locking
4.3.5 Dynamic Tuning
4.4 SWISSTM
4.4.1 SwissTM Overview
4.4.2 Design philosophy
4.4.3 Locking granularity
4.4.4 Contention Manager – Algorithm
4.5 STM FEATURE COMPARISON
5 CHAPTER 5: EMPIRICAL STUDY
5.1 EXPERIMENTAL PLATFORM
5.2 STAMP BENCHMARK
5.2.1 STAMP – Design
5.2.2 STAMP – Applications
5.3 APPLICATION TM CHARACTERISTICS
6 CHAPTER 6: EMPIRICAL RESULTS
6.1 A FIRST-ORDER RUNTIME ANALYSIS
6.2 ANALYZED METRICS
6.2.1 Aborts per Commit (ApC)
6.2.2 Transaction Retry Rate
6.3 VALIDITY THREATS
6.3.1 Internal Validity
6.3.2 External Validity
7 CHAPTER 7: DISCUSSION AND RELATED WORK
CONCLUSION
FUTURE WORK
REFERENCES