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Table of contents
Acknowledgment
Contents
List of Figures
List of Tables
Notations
Résumé long en français
Introduction
Background and motivation
Research Contribution
Organization of the thesis
1 MEMS resonant sensors and electronic interface
1.1 MEMS resonator model
1.2 Resonant MEMS architectures and sensing mode
1.2.1 Resonant sensors based on a single resonator sensors
1.2.1.1 Open Loop sensing mode
1.2.1.2 Closed Loop sensing mode
1.2.2 Duffing nonlinearity effect on single resonator sensors
1.2.3 Open loop vs. closed loop
1.2.4 Discussion
1.2.5 Resonant sensors based on weakly-coupled resonators
1.2.5.1 Resonant sensors based on mutually-injection-locked oscillators
1.2.5.2 Resonant sensors based on mode-localization oscillators
1.2.6 Duffing nonlinearity effect on sensors based on weakly coupled resonators
1.3 Global comparison
1.3.1 Optimum output metric in the linear oscillation regime
1.3.2 Optimum output metric in the nonlinear oscillation regime
1.3.3 Conclusion
1.4 Bilinear amplitude-atrio output metric
1.5 Literature on the analog to digital ratiometric interface
1.5.1 Readout interface requirements
1.5.2 One step approach
1.5.3 Two steps approach
1.5.4 ADC as voltage divider
1.5.5 Demodulator
1.6 Conclusion
2 Ratiometric analog to digital interface based on sigma delta modulator
2.1 Introductionn
2.2 Operating principle and resolution of a sigma delta converter
2.2.1 Operating principle
2.2.2 Metrics and definitions
2.2.3 Resolution
2.3 Modulator architecture selection
2.3.1 Domain: discrete time vs continuous
2.3.1.1 Coefficient sizing and trimming with frequency
2.3.1.2 Thermal Noise
2.3.1.3 Jitter
2.3.1.4 Switch non-idealities
2.3.1.5 Power consumption
2.3.1.6 Conclusion
2.3.2 Single-bit vs. multi-bit quantizer
2.3.3 Loop filter order
2.3.4 Loop topology
2.3.5 Conclusion
2.4 Modulator coefficients
2.4.1 Feedback-coefficient b1
2.4.2 Integrator-coefficients a1 and a2
2.4.3 Simulation results and conclusion
2.5 System level consideration and electrical modeling of the analog blocks
2.5.1 Noise
2.5.2 Integrator non-idealities and optimum OTA specifications
2.5.2.1 OTA finite DC gain
2.5.2.2 Limited slew-rate and gain-bandwidth of the OTA
2.5.2.3 Saturation
2.5.3 Specifications of the analog blocks
2.5.4 Model implementation
2.5.5 Simulation results
2.6 Conclusion
3 Circuit level design of the sigma delta modulator
3.1 Switch
3.2 Operational transconductance amplifier ’OTA’
3.2.1 OTA design comparison
3.2.2 gm/Id design considerations
3.2.3 Folded cascode OTA design
3.3 Bias circuit
3.4 Common mode feedback control circuit
3.5 Integrator
3.5.1 Parasitic insensitive integrator
3.5.2 1-bit DAC input integrator
3.6 Compartor
3.7 Feed forward coefficients
3.8 Non overlapping clock
3.9 Conclusion
4 Post layout simulation results
4.1 Introduction
4.2 Switch
4.3 Operational transconductance amplifier ’OTA’
4.3.1 Nominal simulation
4.3.2 PVT simulation
4.4 Capacitor bank
4.5 Comparator and Non overlapping clock
4.6 Modulator
4.6.1 PVT simulation
4.7 Conclusion
Conclusion and perspectives
Appendices
A Parametric analysis of nonlinear duffing resonator
B Noise shaping
C Integrator transfer function
D VerilogA
D.1 OTA
D.2 Comparator
D.3 Save data
E Temperature aware MILO sustaining electronics
E.1 Introduction
E.2 Current to voltage temperature aware amplifier
E.2.1 Design consideration
E.2.2 Proposed transimpedance amplifier and its operating principle
E.2.3 PVT simulation results
E.2.3.1 ac analysis
E.2.3.2 Input impedance
E.2.3.3 Linearity
E.2.4 Discussion
E.3 Voltage to voltage temperature aware amplifier
E.3.1 Operating principle
E.3.2 Optimization methodology
E.3.2.1 Input differential-pair biasing condition
E.3.2.2 Chanel length effect
E.3.2.3 Comparison of the proposed amplifier with the ordinary active load amplifier
E.3.3 Discussion
E.3.4 Complementary implementation of the proposed temperature aware amplifier
E.4 A 105 dB temperature aware two stages transimpedance amplifier
E.5 Temperature aware two stage miller compensated DOTA
E.6 Sample and hold peak detector
E.7 Conclusion
Bibliography
