Unipolar and bipolar technology: MOSFET and IGBT
For applications that requires blocking voltages higher than 1kV, the Si MOSFET technology exhibits some serious limitations . As shown in Fig. 1.13, the current path is allowed by the enhancement of a unipolar 𝑛 charge channel in the 𝑝 layer beneath the gate oxide. The role of the epitaxial 𝑛− layer, shown in Fig. 1.13, is to withstand the blocking voltage of the device during the off-state. In reverse mode, the depletion region expands through the epitaxial layer. In order to contain the electrical field in this region, the 𝑛− region needs to be lightly doped. As a consequence, the depletion region is more extended, and the thickness of the epitaxial layer has to be increased accordingly in order to avoid avalanche phenomena in pinch-through or reach-through . Briefly, the thicker the epitaxial layer, the lower the doping level and the higher the breakdown voltage.
Electro-magnetic Interferences (EMI) Issues
The SiC-MOSFET unipolar components show far quicker switching times than the Si-IGBT bipolar components due to the absence of minority carriers scattered in the drift layer. But such assets do not come without any setback. Indeed, the high 𝑑𝑣/𝑑𝑡 and 𝑑𝑖/𝑑𝑡 slopes are disruptive. First, they provoke the premature ageing of electrical machines and insulators. They also increase the interaction between the driver and the power circuits due to the transfer capacitor 𝐶𝐺𝐷 of the transistor. Eventually, they disturb both the system and the surrounding electronics devices in terms of electromagnetic compatibility. In other words, they make it harder to comply with electromagnetic standards owing to the common mode current.
The SiC technology allows higher switching frequencies than Si counterpart. For instance, the selected SiC-MOSFET is able to operate up to 100kHz according to the datasheets, whereas the selected Si-IGBT is limited to the tenths of kHz . However, such advantages raise issues. First, parasitic capacitors admittances and stray inductors impedances increase with frequency. Then, phenomena like LC resonant circuits and the related oscillations, or undesired coupling (capacitive and mutual), become more significant.
In order to analyse the high frequency behaviour within a switch-based power converter, idealized waveforms are frequently used to simplify the modelling of converter behaviour . The switching devices are often modelled as voltage or current trapezoidal signal generators, i.e., a periodic pulse train with frequency 𝑓𝑠, pulse width 𝜏 , and finite rise and fall times 𝑡𝑟 and 𝑡𝑓 (Fig. 1.17(a)). The duty ratio 𝐷 is given by 𝐷=𝜏 /𝑇, where 𝑇 = 1/𝑓𝑠 is the period of the waveform. The characteristics of their spectra are widely used to understand the underlying relationships between time-domain waveform parameters and spectral content. With such approximation, the overshoots and the ringing phenomena are neglected.
Any trapezoidal signal presents a spectrum similar to the one displayed on Fig. 1.17(b). This spectrum has a bound or “envelope” which may be described (on logarithmic axes) by a series of linear asymptotes having gradients of 0 dB/dec, −20 dB/dec, and −40 dB/dec, at the corner frequencies of 1/𝜋𝜏 and 1/𝜋𝑡𝑟, in increasing order of frequency.
If the switching frequency increases then the spectrum is translated towards the right, i.e. up to higher frequencies. When the EMI standards are considered, it comes clear that it raises compliance problem, the standard template may not be respected.
As showed in –, the higher transition slope of current and voltage across the device leads to a remarkable increase of the harmonic content. In , the double pulse test (Fig. 1.15) was performed for three combinations of the semiconductor transistor (device under test) and the free-wheeling diode, namely an all-Si combination, a Si transistor (IGBT) and a SiC-Schottky diode combination, and an all-SiC. The magnitude spectra and the envelopes of the commanded device current and voltage waveforms in the set-up of Fig. 1.15 are shown in Fig. 1.18.
Si IGBT/ SiC MOSFET Experimental Comparison on a Boost converter
Prior to focusing on a specific power converter design, it is required to determine the peculiarities of the SiC MOSFET technology, not only in terms of voltage and current ratings, dynamics and static behaviours but also when it comes to implementing it in a power electronics environment. Ratings and static characteristics are generally available on the data sheet and they can be reproduced through experimental tests (output characteristic, transfer characteristic, on resistance …).
Besides the literature results provided in Fig. 1.16 and Fig. 1.18, experimental tests have been carried out at the laboratory on test benches on a boost converter. In terms of components, a Si Trench IGBT Modules SKM 195GB126D (220 A – 1200V) and a SiC-MOSFET Half-bridge Modules CREE CAS100H12AM1 (168A – 1200V) were selected mainly because of their common wide use on the market and the similar ratings. The following experimental tests are intended to verify the considerations made concerning the performances of the two devices.
In terms of converter, it is necessary to choose a circuit renowned as a reference among the power electronics community and highly widespread in the industrial field. It should be a quite simple topology so that the carried investigations can only focus on the active component behaviour and do not extend neither to the conversion process nor to the control. Consequently, it was implemented a boost converter with the following characteristics: input voltage : 𝑉𝑖𝑛=230𝑉, output voltage:
output power: 𝑃𝑜=3𝑘𝑊.
𝐿=8.7 𝑚𝐻 𝐶𝑜=44 μF.
DC/DC power converters for Starter applications in a MEA
As already discussed in the first chapter, in the particular case of the MEA, Variable Speed Generators are used to suppress the mechanical gearboxes in order to increase the reliability of the high power sources. The AC network voltage of these aircrafts and consequently the voltage level of the different DC-buses may vary considerably. The secondary loads are supplied through a DC bus obtained by the rectification, through an Auto-Transformer Rectification Unit (ATRU), of the variable frequency/amplitude AC voltage generated by the Variable Speed Generator (VSG) through an uncontrolled rectifier unit. The voltage value of the DC bus with a nominal voltage of 270V can indeed vary from 230V to 335V. Furthermore, the electrical loads need to be connected through an input filter in order to decouple each load form the other and to comply with the aeronautical EMC standards for conducted disturbances that may occur on DC bus.
DC/DC Step-up converters topologies
The reachable speed of the PMSM is proportional to the maximal available phase voltage magnitude, i.e. the DC voltage upstream the VSI (𝑉𝐷𝐶 in Fig. 2.1(b)). The maximal voltage is determined by the available 𝑉𝐷𝐶 value and the modulation method. In order to extend the range of speed, a traditional flux weakening method could be applied , , which can be realized by applying a demagnetizing d-current in the 𝑑𝑞 frame. However, this method increases the winding copper losses and also risks irreversible demagnetization of the machine core.
In terms of losses, it is preferable to adapt 𝑉𝐷𝐶 to the maximal speed within the application mission profile. When a high speed is required for the most part of the operating cycle, a step-up DC/DC converter is often employed. The classical step-up architectures are presented in the following subsections.
The first studies about impedance fed converters date back to 2003. In , a new topology of DC/AC inverter was described, shown in Fig. 2.4, for electrical traction which introduces the possibility to step up and down the AC output voltage amplitude by only commanding the inverter switches.
The traditional three-phase VSI has six active configurations and two zero states, where the load terminals are shorted through either the lower or upper three devices, respectively.
The three-phase Z-Source inverter, composed by the assembly of the Z-Source converter and the inverter, is featured by an additional configuration, called shoot-through, which occurs during the zero-state configurations, where one or more legs of the inverter are shorted out and 𝑉𝐷𝐶=0. The 𝑑𝑐𝑐 duty cycle of the shoot-through determines the boosting factor of the 𝑉𝐷𝐶 voltage: 𝑉𝐷𝐶𝑉𝑖𝑛=11−2𝑑𝑐𝑐 (2.12).
A visible disadvantage of this topology comes from the presence of the diode at the input terminal. Because of the input discontinuous input current, the input filter shall provide a bigger attenuation of the harmonic content at the switching frequency to comply with the application standards, which leads to a bigger size.
The same authors, in a successive work , showed some evolutions of the original Z-Source inverter topology, which solve several problems like the input current discontinuity or the excessive voltage/current stress through the converter passive elements. For the considered application, the voltage fed Quasi Z Source Inverter (QZSI) shown in Fig. 2.5 is particularly suited.
The operating principles of the QZSI are pretty the same, with the same voltage gain expressed in (2.12). On the other hand, this topology is featured by a continuous input current because of the 𝐿1 inductor. As it will be shown in Section 2.3.2, with an opportune coupling of the two inductors it is possible to totally suppress the current ripple at the switching frequency, with a consistent gain on the size of the input filter .
Due to the shoot-through state, this topology is unsuitable for the generation of the inverter switches command signals through a Pulse Amplitude Modulation (PAM), which is an interesting alternative to the Pulse Width Modulation (PWM) . The PAM could bring several benefits to the overall system performances, especially at high speeds. Such strategy allows indeed to considerably reduce the switching occurrences of the inverter transistors, with a consequent reduction of the power losses. Moreover, it enables to reduce the high frequency harmonic content conducted in the network which could be harmful for the stator windings and increase the voltage gain on the AC side.
A possible solution to overcome such limitation consists in the topology proposed in Fig. 2.6, where the power load (inverter/PMSM) is connected to the 𝐶1 converter, as in .
DC/DC Step-up/down converters topologies
When the actuator is composed by a step-up converter and the inverter, if a low mechanical speed is required, the amplitude of the motor phases AC voltage is achieved by lowering the inverter PWM modulation index. Anyway, the high voltage stress on the inverter switches and the recurrent commutations could remarkably decrease the efficiency of the inverter.
The addition of a DC/DC converter in the power chain of actuators is also proposed in ,  by applying a PAM control, which permits to reduce the VSI losses and to improve the actuators performances at high speeds.
In case of constant DC-bus voltage, the PMSM has to be designed according to its speed limit in order to ensure the current controllability of the motor at the DC-bus voltage. In applications like starters, the used actuators equipped with PMSM operate at low speeds in major part of the mission cycle and at higher speeds occasionally during a short interval , . At low speeds, a DC inverter input voltage lower than the input DC-bus voltage is required. At higher speeds, the inverter input voltage should be increased; hence the bus voltage boosting is required. The operating cycle can be assumed similar to the one shown in Fig. 2.7, during which a boost conversion is required in a short interval of the working cycle period 𝑇𝑐𝑦𝑐𝑙𝑒.
MOSFET switching behaviour
The MOSFET behaviour during the switching transients is strongly influenced by the intrinsic capacitances of the device.
The following analysis is carried out under the condition of an inductive current, since it is the most common case in practice. The driver circuit is assumed to deliver constant voltages, providing 𝑉𝑑𝑟 in turn-on and 0 in turn-off, and 𝑟𝑔 is the gate-resistance composed by the series connection of the internal gate resistance (provided by the constructor datasheet) and the external driver resistance.
In a bi-directional boost converter, the low MOSFET 𝑆1 commutates in hard-switching, hence the drain-source voltage 𝑣𝐷𝑆 abruptly changes between the conduction voltage drop to/from the nominal reverse voltage 𝑣𝐷𝑆𝑆1(𝑜𝑓𝑓)=𝑉𝑜.
Thanks to the conduction of the high diode during the dead band time, the high MOSFET 𝑆2 transition occurs instead in soft switch, i.e. the reverse voltage during the commutation amounts to the only diode bias voltage 𝑣𝐷𝑆𝑆2(𝑜𝑓𝑓)=−𝑉𝐷. The switching energy loss in 𝑆2 results indeed widely lower than the 𝑆1 one.
Consequently, only the switching behaviour of 𝑆1 is discussed.
Table of contents :
1 Power Electronics Systems for Embedded Applications
1.2 Embedded application in the transportation sector
1.2.1 More Electric Aircraft (MEA)
1.3 New opportunities: Wide Band-Gaps Devices
1.3.1 SiC and Si technology comparison
1.3.2 Unipolar and bipolar technology: MOSFET and IGBT
1.3.3 Electro-magnetic Interferences (EMI) Issues
2 DC/DC Power Conversion in an Embedded Powertrain Application
2.2 DC/DC power converters for Starter applications in a MEA
2.2.1 DC/DC Step-up converters topologies
2.2.2 DC/DC Step-up/down converters topologies
2.3 Proposed QZS step up/down DC/DC converter topology and its modelling
2.3.1 Operating principles
2.3.2 Input ripple suppression
2.3.3 QZSBC experimental validation
3 DC/DC Power Converter Design
3.2 DC-DC Boost Converter Design
3.3 Active components
3.3.1 MOSFET conduction behaviour
3.3.2 MOSFET switching behaviour
3.3.3 Freewheeling Diode
3.3.4 Thermal analysis
3.4 Passive Components
3.4.1 Magnetic component design
3.4.2 Output Capacitor
3.4.3 EMI Filter
4 Dynamical Analysis and Control Strategy of a DC-DC converter
4.2 Dynamical model of a DC/DC switched converter
4.3 Boost dynamical behaviour
4.3.1 Frequency domain stability analysis
4.3.2 Boost dynamical analysis
4.4 Control strategy for power disturbance rejection
4.4.1 Inner Loop: Peak Current Mode Control
4.4.2 Energy loop
4.5 Capacitor design for load transient rejection
4.5.1 Evaluation of the minimal value of 𝐶𝑜 in step-up load transient conditions
4.5.2 Evaluation of the minimal value of 𝐶𝑜 in step-down load transient conditions
4.5.3 Evaluation of the minimal value of 𝐶𝑜 for a smooth load transient condition
4.6 Stability issues related to the insertion of the differential input filter
4.6.1 Stability of cascaded sub-systems
4.6.2 Interaction between LC input filter and Boost converter: small-signals domain analysis
4.6.3 Interaction between LC input filter and Boost converter: discrete time domain analysis
5 Multi-Objective Optimization of a DC/DC Boost Converter
5.1 Introduction: Optimization Problem
5.1.1 Figure of Merits
5.1.2 Optimization problem: Design Variables Space and Performance Space
5.1.3 Genetic Algorithms: NSGA II
5.2 Multi-objective optimization of a DC/DC converter
5.2.1 Design Space and parameters
5.2.2 Objective functions
5.2.3 Constraints Functions
5.2.4 Optimization results
5.3 Experimental results