Possible Solutions in the Roadmap
Figure 1.7 shows the ITRS future projection about diﬀerent technologi-cal innovations in diﬀerent stages of growth: research required, development underway, pre-production and further continuous improvement. As already discussed, in the last decade, the following technology innovations were suc-cessfully incorporated in the existing silicon process flow: enhanced mobility and high-field transport via strain, enhanced quasi-ballistic transport (via short gate length and strain), high- gate dielectric, metal gate electrode, and Fully depleted SOI MOSFET.
Planar Fully Depleted Silicon On Insulator (FDSOI) MOSFETs (Figure 1.8) have been well known for a long time for their advantages over the bulk coun-terpart: good electrostatic control enabling lower VDD (for example ), undoped/lightly doped channel leads to reduced random dopant fluctuations and hence reduced process variability, reduced source-substrate leakage due to presence of buried insulator layer, and most importantly, maintaining con-sistency with existing fabrication processes (e.g. the 28 nm bulk technology).
At the same technology node, Ultra Thin Body and Buried oxide (UTBB) FDSOI transistors allow to have shorter channel lengths than bulk devices. Body biasing (applying voltage to the substrate) the FDSOI device eﬀectively makes it act like a double gate device (thanks to the very thin buried ox-ide layer) leading to much lower leakage and improved performance. Even in recent years the FDSOI MOSFETs have been the subject of active re-search   and considered as viable alternatives to bulk CMOS, oﬀering competition to other new technologies like FinFETs .
A major deviation from the planar transistors are the Multi-Gate MOS-FETs, either bulk or SOI. Mulitple gates, particulalry the double and triple gate SOI FinFETs were the topic of extensive exploration in the last decade, al-though other possibilities: like quadruple gates, gate-all-around (GAA) MOS-FETs and bulk FinFETs have also been researched  . Figure 1.9 shows three dimensional schematics of double and triple gate FinFET devices on fabricated on SOI. These devices, due to the presence of more than one gate, oﬀer higher drive currents and tighter gate control of the channel electrostatics leading to excellent short channel performance. Accordingly, the industry has already entered the production phase going with Intel’s tri-gate FinFETs .
ITRS 2011 lists alternative channel materials (ACM), namely III-V and Ge based MOSFETs as currently being pursued with a goal to enter produc-tion in the next 5-10 years . Indeed, of late, a lot of research has been directed towards using these high mobility materials as MOSFETs channels. For example, Figure 1.10 depicts the increase in the number of publications concerning III-V MOSFETs in the last few years, hinting at the serious con-sideration of these devices by the academia as well the industry.
Motivation for ACM/Why III-V?
There has been, in fact a long interest in alternative channel materials for replacement of Si as channel material in transistors. The first transis-tor realized (point contact type) in 1947 was germanium based. As early as 1966, InAs channel transistors were proposed  and in 1991 Ge CMOS was demonstrated . But the growth of III-V/Ge CMOS for logic remained hindered because of several technological problems (e.g. Fermi level pinning), and high mobility materials were rather mostly used for HEMT devices (which are impractical for use as logic devices due to their large gate leakages). In the last decade, they have made a comeback as some of the stumbling blocks have been dealt with (for example unpinning the Fermi level using Ga2O3/Gd2O3 as gate oxide [28,29], achieving good quality thermally grown GeO2  etc.).
As explained in subsection 18.104.22.168 there is a need to lower VDD, while main-taining, or if possible, increasing the device speed. A channel material having higher carrier mobility compared to Si can achieve this goal. In this view, III-V/Ge MOSFETs are strong candidates for high performance (HP) logic as they can oﬀer lower power (approaching VDD = 0.5 V) at speeds similar to, or even higher than the Si counterparts due to their inherent good transport Comparison of HP (high performance), LOP (low operating power), LSTP (low standby power), and III-V/Ge Technologies according to ITRS 2012 re-port  is shown in Table 1.1 in terms of device speed, dynamic power and static power dissipation. III-V/Ge devices with their higher speed and lower dynamic power, are expected to outperform Si HP devices.
Table 1.2 lists some material properties of certain materials as candidates for MOSFET channel material. As can be seen, what makes germanium and III-V compound semiconductor materials attractive is their much lower eﬀec-tive masses and higher carrier mobilities.
Following Natori’s ballistic model , the injection velocity of electrons in the device is related to the eﬀective mass under non-degenerate conditions as follows :
Hence channel materials with lighter eﬀective masses can provide higher in-jection velocity, vinj in ultra scaled MOSFETs. It has been demonstrated that these materials present greatly improved transport properties with respect to unstrained and even strained silicon .
III-V materials generally have multi-valley bandstructures: A primary valley with low-eﬀective-mass and satellite valleys (L and X) with higher ef-fective mass for electrons. Many III-V materials, for example InxGa 1-xAs grown lattice matched to InP or InAs grown lattice matched to AlSb have very low eﬀective masses in valley as well as large inter-valley energy sep-arations ( L, X which can be increased by increasing the In content) reducing the chances of spillover of electrons from to L valley. This could lead to achieving higher mobilities at both low as well as high applied fields. Figure 1.11 shows the bandstructure of InGaAs.
where m is the DOS eﬀective mass (for electrons in 2D, m = pmt mt = mt), nv is the valley degeneracy and the factor 2 accounts for spin degeneracy. This “DOS Bottleneck” can limit the maximum Ion in the ballistic limit . The contrast of the impact of the eﬀective mass (m ) on the vinj and the DOS as seen from equations 1.3 and 1.4 signifies the trade-oﬀ inherent in these materials.
Table 1.2: Physical properties of some Alternative Channel Materials at 300 K (Taken from )
In addition, the band gaps (Eg) of most of the high mobility channel materials are considerably low. Therefore the leakage currents in these devices are expected to increase exponentially. Also, the high dielectric constant of Ge and III-V materials will result in easier encroachment of the drain electric field into the channel, thereby causing more relative loss of gate control on the channel electrostatics and hence poor device characteristics.
Current Status of ACM Devices
Following the technological improvement and the potential performance increase of devices with Ge and III-V channels, successful fabrication of these high mobility material MOSFETs has already been achieved.
Table of contents :
1.1 State of the art in transistor industry
1.1.1 Limits of scaling
1.1.2 Heterogeneous Scaling and Technology Boosters
1.1.3 Possible Solutions in the Roadmap
1.2 III-V MOSFETs
1.2.1 Motivation for ACM/Why III-V?
1.2.2 ACM Trade-offs
1.2.3 Current Status of ACM Devices
1.3 Need to evaluate SCEs in III-V MOSFETs
1.4 Aim of the Thesis
1.5 Organization of the Thesis
2 Modeling of the channel potential in a MOSFET
2.2 Channel Potential Modeling
2.2.1 Analytical Modeling
2.2.2 Concept of the extra potential in a short channel MOSFET
2.2.3 FlexPDE Numerical Simulation
2.2.4 Comparison: Model Vs Numerical Simulation
2.3 The Question of Boundary Conditions
2.3.1 Impact of the Source/Drain regions on SCEs
2.3.2 Electrostatics: Variation of the minimum of channel potential (top of the barrier)
2.4 Effective Built-In Potential, V effbi
2.4.1 Analytical Modeling of V effbi
2.5 Impact of the Source/Drain doping
2.6 Corrected Short Channel Effects
3 Origin of SCE increase in III-V MOSFETs
3.1 SCEs in III-V MOSFETs
3.2 Quantum Effects and SCEs in Subthreshold Regime
3.2.1 Concept of Dark Space
3.2.2 Simulation Methodology
3.2.3 Simulation Results
3.3 Impact of Material Parameters
3.4 DIBL in Strong Inversion Regime
3.4.1 Effective current and DIBL
3.4.2 Dark space and DIBL in strong inversion
3.4.3 Definition and extraction method of the DIBL in strong inversion regime
3.4.4 Impact of quantum effects and dark space on the DIBL in inversion
3.5 Impact of the architecture on the SCEs
3.5.1 Impact of barrier layers: QWFET Vs thin films
4 Source to Drain Tunneling and III-V MOSFETs
4.1 Leakages in Nanoscale MOSFETs
4.2 Source to Drain Tunneling
4.2.1 The WKB approximation
4.2.2 Effective barrier size modulation
4.3 Source Drain Tunneling and ACM
4.4 Quantum Confinement and SDT
5 Conclusions and Future Perspectives
5.2 Future Perspectives