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**Chapter 2 ****12V Non-Isolated Zero Voltage Switched Complimentary-Controlled Full Bridge with Self-Driven Synchronous Rectification for High Frequency, High Current VRM Application**

The topology used in this work is 12V Non-Isolated Zero Voltage Switched Complimentary-Controlled Full Bridge with Self-Driven Synchronous Rectification. This topology was presented by Dr. Jinghai Zhou in [2.1]. The topology proposed by Dr. Zhou is a “buck-derived soft switching topology with duty cycle extension and SR device self-driven capabilities”. Shown below is a circuit diagram of the 12V non-isolated zero voltage switched complimentary-controlled full bridge with self-driven synchronous rectification from [2.2].

This topology uses complementary controlled bridge (CCB) self driven design to allow for soft switching. The overall benefit from this topology is its ability to allow for reduction of switching losses allowing for higher switching frequencies to be used. This will reduce the size of the converter and reduce the number of output capacitors needed.

**Principles of Operation**

The detailed circuit operation of this design is thoroughly discussed in [2.2]. For the purposes of this work, a small overview from [2.2] of circuit operation is given with expanded analysis given to the areas related to the effect of leakage inductance on the circuit performance. Shown below is the control strategy of the 12V non-isolated ZVS self-driven scheme.

Mode 1: to-t1: Switches Q1 and Q2 are on during this period. This means that the gate of Q5 is connected to the input voltage and is on during this period. With Q2 and Q5 on, the gate signal of Q6 is connected to ground and off during this period. This period is an energy transfer period; the energy is transferred to the output from the transformer.

Mode 2: t1-t2: At t1, Q2 is driven off by the external driver. The output current is reflected to the primary side to charge the output capacitor of Q2 and discharge the capacitor of Q4. The input capacitor of Q6 is also charged during this period because of its connection to point A.

A dead time is required to allow for the voltage of point A to reach the input voltage to allow for ZVS switching of Q4 in the next period. The required dead time is given below

This dead time will insure ZVS of Q4 which saves switching loss and helps this topology push the switching frequency. The number of turns in the transformer is represented by *n** _{p}* , the equivalent capacitive network

*C*

*is equal to*

_{eq}*C*

*=*

_{eq}*C*

_{oss}_{_}

_{Q}_{2}+

*C*

_{oss}_{_}

_{Q}_{4}+

*C*

_{iss}_{_}

_{Q}_{6},

*V*

*is equal to the input voltage, and*

_{in}*I*

_{o}_{min}is equal to the minimum load current required to achieve ZVS in this scheme.

Mode 3: t2-t3: During this mode of operation Q4 is turned on with zero voltage and the energy stored in the leakage inductance of the transformer freewheels through Q1 and Q4. Q5 and Q6 are also on during this period and a freewheeling current path is seen in the current doubler loop.

Mode 4: t3-t4: Q1 is driven off at t3. The reflected loop inductance of the current doubler and leakage inductance resonate with the output capacitors of Q1, Q3 and the input capacitor of Q5. To achieve ZVS for Q3, two criteria must be met. The leakage inductance must produce enough energy to charge and discharge the equivalent capacitive network created by Q1, Q3, and Q5. The minimum output current to achieve ZVS is derived by using:

The second requirement to achieve ZVS is to use a dead time between Q1 and Q3 of one fourth the resonant period to allow for Q3 to be turned on while achieving ZVS. This dead time is given as

Modes 5-8: t4-t8: The second half period occurs during this period and follows the same operation but with reversed polarity.

**Effects of Leakage Inductance on Circuit Performance**

The leakage inductance of the transformer and current doubler affect the performance of the 12V Non-Isolated Zero Voltage Switched Complimentary-Controlled Full Bridge with Self-Driven Synchronous Rectification significantly. The leakage inductance results in duty cycle loss, affects ZVS operation points, and affects the body diode conduction loss of the current doubler switches. In this section, the effects of the leakage inductance will be studied the benefits of reduced leakage will be explored.

**Duty Cycle Loss**

The first affect of leakage inductance is duty cycle loss. Shown below is the schematic and waveforms of the transformer windings and voltages in the 12V Non-Isolated Zero Voltage Switched Complimentary-Controlled Full Bridge with Self-Driven Synchronous Rectification topology.

The secondary voltage of the transformer loses duty cycle as a result of the leakage inductance of the transformer. The time it takes the primary current to switch polarities is responsible for this duty cycle loss. Looking at the primary current waveform during the duty cycle loss period a formula for duty cycle loss can be obtained.

As the switching frequency and load current are increased the duty cycle loss also increases. To minimize the duty cycle loss, the leakage inductance should be improved. This will allow for a larger range of operation. Shown below are plots showing the duty cycle loss related to various load currents and switching frequencies. Another factor in the loss of duty cycle is the winding resistance of the transformer and loop inductance. The transformer and loop resistance drop a small portion of resistance, but for this case only the duty cycle loss resulting from leakage inductance is studied.

The duty cycle loss plot above shows how as the load current increases, so does the duty cycle loss. As was discussed in chapter 1, it is expected that the current demands of the future microprocessors will increase. This means that something will have to be done to reduce the duty cycle loss for this topology; one means of doing this is by reducing the leakage. The plot below tells a similar story, if the switching frequency of this topology is to be increased in the future, the duty cycle loss must be decreased, lower leakage again is a logical solution.

This section discussed the duty cycle loss related to leakage inductance for the chosen topology; there are alternate solutions to reduce the duty cycle loss other than reducing the leakage. The next section will explain why reduced leakage would be a beneficial solution not only for duty cycle loss but for body diode conduction loss. By reducing the leakage inductance, the duty cycle loss problem and body diode conduction loss problems can be solved.

**Body Diode Conduction Loss**

A major source of loss in the 12V non-isolated zero voltage switched complimentary-controlled full bridge with self-driven synchronous rectification is related to the body diode conduction losses in the current doubler switches. The body diode conduction period and loss was explained in [2.4] and [2.2]. The switching diagram below from [2.1] shows the body diode conduction period. When Q1 is driven to be off and the equivalent capacitive network resonates with the leakage inductance until the voltage reaches zero. Q5 continues to conduct current until the transformer completely switches polarity, during this period, the body diode of Q5 conducts current. The same process occurs for Q6 in the opposite interval.

Chapter 1 Introduction

1.1 Background and Research Objectives

1.2 Thesis Outline

Chapter 2 12V Non-Isolated Zero Voltage Switched Complimentary-Controlled Full Bridge with Self-Driven Synchronous Rectification for High Frequency, High Current VRM Applications

2.1 Principles of Operation

2.2 Effects of Leakage Inductance on Circuit Performance

2.3 Duty Cycle Loss

2.4 Body Diode Conduction Loss.

2.5 Affect of Leakage Inductance on ZVS

2.6 Summary

Chapter 3 Improvements of 12V Non-Isolated Zero Voltage Switched Self-Driven Scheme VRM with Low Leakage Magnetics Design

3.1 Leakage Inductance and Winding Resistance Calculations

3.2 Discrete Magnetics Components

3.3 Original Integrated Magnetics Concept and Design

3.4 Cost Effective Integrated Magnetics Design

3.5 Improved Leakage Inductance Design

3.6 Improved Magnetics Design Implementation

3.7 Winding Loss for Integrated Magnetics

3.8 Experimental Results and Summary

Chapter 4 Future Work

4.1 Alternate Winding Configuration

4.2 Surface Mount Magnetic Components.

4.3 Coupled Magnetic Solutions

4.4 Alternate Topology Solutions

References

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