Fabrication of empty cavities on Si refilled by III-V crystals

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Requirements for self-aligned MOSFETs

Extensive investigations exist in the literature on the fabrication and characterization of InGaAs n-MOSFETs. Numerous device architectures have been proposed and the vast majority of them were designed with the following guideline: find a device architecture which will simplify the process as much as possible while maximizing the device perfor-mance in order to experimentally prove the high expected potential of III-V MOSFETs for future CMOS applications.
This approach is very valuable for the scientific and industrial community as it allows to demonstrate InGaAs-based hardware exceeding the performance of Si MOSFETs. In the device architecture which appeared to be the most successful to achieve record per-formances [20–23], the S/D regions are formed first either by etching an already existing blanket layer of highly-doped InGaAs or by selectively growing it ; then the gate region is defined by lift-off with a large overlap with the contact regions. The resulting device has S/D regions self-aligned to the channel which ensures a low access resistance and thus a high performance, but not self-aligned to the gate.
All those “performance-optimized” architectures have in common the fact that they do not meet the requirements for large-scale manufacturing of CMOS circuits. They typically cannot be scaled down to aggressive pitch and contain a large and uncontrollable gate to S/D overlap. Nevertheless, they represent today’s state-of-the-art InGaAs n-MOSFET performance [20], exceeding that of production Si n-MOSFETs.
In this thesis, it is decided from the beginning to focus on enabling InGaAs MOSFETs integration into CMOS platforms rather than using any means for achieving record perfor-mance. Therefore, the priorities are to first demonstrate CMOS-compatible self-aligned InGaAs MOSFETs on Si, then optimize the process for higher performance. The results will show record performance among all existing CMOS-compatible InGaAs MOSFETs on Si, but still behind that of “performance-optimized” InGaAs MOSFETs architectures on native III-V substrates.
The baseline device architecture selected in this work matches IBM’s Alliance 22 nm gate-first (GF) fully-depleted silicon on insulator (FDSOI) technology [24], shown in Fig. 1.2. The high-k metal-gate (HKMG) stack is first formed on the channel, followed by dry etching of the gate. Ultra-thin spacers are formed on each side of the gate acting as a lateral isolation to the S/D. An in-situ doped selective epitaxy of Si and SiGe raised S/D (RSD) is carried out on n- and p-MOSFETs respectively. Dopants from S/D are diffused underneath the spacers via a high temperature spike anneal. Finally, self-aligned nickel silicides are formed on the doped RSD, completing the front-end-of-line (FEOL) process. Tungsten plug contacts are realized and the back-end-of-line (BEOL) interconnects com-plete the chip fabrication. With this integration flow, the entire device is fabricated in a self-aligned way around the gate line. No lithography steps are required to position the S/D regions relative to the gate, and the gate to S/D overlap can be controlled by the spacer thickness and dopant diffusion.
In Chapter 3, it is proposed to adapt this baseline architecture for InGaAs n-MOSFETs by developing InGaAs-compatible HKMG stacks, replacing Si RSD by in-situ n-doped InGaAs RSD and by introducing self-aligned Ni-InGaAs metal contacts. Direct metal contacts to InGaAs for connecting the devices to the BEOL interconnects are also studied as an alternative to Ni-based alloyed contacts.
Based on those developed process modules, CMOS-compatible self-aligned InGaAs MOSFETs are fabricated and characterized in Chapter 4. Various device architectures are studied: bulk vs on-insulator, planar vs fins, GF vs replacement metal-gate (RMG), junction-less (JL) devices vs MOSFETs.

Hybrid CMOS circuits

The development of a low-power high-performance CMOS technology based on high mo-bility channels cannot be made exclusively out of InGaAs as channel material.
Firstly, InGaAs has a poor hole mobility, lower than that of Si, and cannot act as a “high-mobility” p-type MOSFET. The use of SiGe is currently the most promising option for future CMOS technologies [5], outstanding device performance is already demonstrated in p-type SiGe fin-based MOSFETs (FinFETs) [25–27]. It is therefore envisioned to build a hybrid CMOS technology with n-type InGaAs MOSFETs and p-type SiGe MOSFETs, where the In- and Ge-contents would be increased from generation to generation, providing higher mobility, higher strain and lower operating voltage. Another potential candidate for high-mobility p-type MOSFETs is galium-antimonide (GaSb), but it does not have a better hole mobility than Ge, has a much larger lattice mismatch and has a poor thermal stability limited to about 450 C. For those reasons, an hybrid InGaAs/SiGe technology remains the preferred approach.
Secondly, a CMOS chip does not only contain low-power high-performance core logic devices. It also needs high-voltage components such as I/O devices or protection circuits against electrostatic discharges. Those components are based on Si MOSFETs which can sustain much higher voltages than the core logic devices. Lower bandgap materials such as InGaAs or SiGe are not good candidates to realize those devices as a high breakdown voltage requires a wide bandgap. Therefore, a high-mobility CMOS technology is a true hybrid platform which not only needs to integrate InGaAs with SiGe but also with Si, on Si.
Numerous technology integration challenges have to be tackled. Firstly, the fabrica-tion of MOSFETs on Si, SiGe and InGaAs requires very different thermal budgets. Si needs about 1100 C, SiGe requires around 950 C at 25%-Ge, 750 C at 50%-Ge and maybe 500 C for pure Ge, while InGaAs is limited to approximately 600 C. The boundary con-ditions for those thermal budgets have a different nature, some are related to a minimum temperature to efficiently activate dopants, some to obtain reliable gate stacks, some are limited by dopant diffusion or by intrinsic material degradation. Secondly, those three materials have very heterogeneous chemical properties. Most of the standard wet cleans and dry etching modules have to be adapted to provide the right selectivities to each material. For instance, the standard SC-1 and SC-2 for Si wet cleaning steps or the usual gate dry etching steps attack InGaAs at a very high rate. Removing these cleaning steps might largely impact the standard processes to fabricate Si and SiGe devices, yet com-promising performance should be avoided. Finally, the method used to integrate InGaAs on a Si platform should not limit density scaling. The main driving force behind the development of advanced technology nodes is the increase of the number of transistors per unit area. A transition to InGaAs-based n-MOSFETs should support the develop-ment of smaller, denser and faster chips ; it cannot compromise integration density. Each material integration scheme discussed in the introduction section 1.2 or in Chapter 2 has its own boundary conditions in terms of integration density which need to be jointly eval-uated with the circuit designs. Indeed, it might not be required to replace every single low-power high-performance Si n-MOSFET by its InGaAs counterpart. In some possible scenarios, only a few percent of InGaAs devices might need to be introduced, which could completely change the preferred material integration method.
Very few reports exist on hybrid InGaAs/SiGe CMOS technology platforms as it is a complex and challenging milestone. Two circuit architecture are envisioned: 2D co-planar and 3D monolithic circuits. The 2D co-planar architecture is the industry-standard approach where both types of devices are co-processed simultaneously, at the same level on the wafer. In the case of the 3D monolithic architecture, two (or more) layers of transistors are stacked on top of each other, sharing a common BEOL. These two approaches have very different requirements in terms of thermal budget, number of lithography steps, process complexity and density of integration. These two architectures have already been demonstrated in the form of 2D co-planar InGaAs/Ge MOSFETs bonded on a Ge substrate [28], 3D monolithic InGaAs/Ge inverters on Ge wafers [29] and 3D monolithic InGaAs/SiGe ring-oscillators on Si substrates [30]. Although those demonstrations pave the way towards a manufacturable InGaAs/SiGe CMOS technology, they are using very primitive fabrication processes and low thermal budgets to circumvent the real challenges of co-integration, which results in poor performance compared with what can be achieved in stand-alone InGaAs MOSFETs.
In the last Chapter 5, we will address both 2D co-planar and 3D monolithic circuit architectures to demonstrate hybrid InGaAs/SiGe CMOS circuits on Si. DWB will be used to establish a primitive 2D co-planar platform, which will then be further developed into dense static random access memory (SRAM) arrays obtained by local selective epi-taxy, featuring a full-scale process for the n-MOSFETs. Finally, DWB enables the 3D monolithic integration of InGaAs n-MOSFETs on state-of-the-art SiGe p-MOSFETs, with an independently optimized full-scale fabrication process for each device layer achieving excellent performance.

Thesis: Organization and relation to published work

The technical work is presented in four chapters following the main different aspects of the realization of a hybrid InGaAs/SiGe CMOS technology platform: Substrates, Process Modules, Devices and Circuits. The next paragraphs link the content of the technical chapters to the most relevant published work. A detailed list of published contributions can be found in Appendix A. Chapter 2, “Substrates”, presents all the material developments performed in this work to integrate thin layers of InGaAs on Si substrates for subsequent device and circuit fabrication. This chapter is composed of two parts on wafer bonding of blanket layers, and local selective epitaxy in empty oxide cavities. The work on wafer bonding is mainly supported by reports at the International Electron Device Meeting [31], in Applied Physics Letters Materials [11], and at the VLSI Technology Symposium [13]. The part on selective epitaxy in empty oxide cavities refers to a report at the VLSI Technology Symposium [32].
Chapter 3, “Process Modules”, focuses on the most relevant process modules for the realization of high-performance self-aligned InGaAs MOSFETs. The first part presents development of HKMG stacks on InGaAs, the second part reports on the developments of self-aligned S/D regions and metal contacts. The work on HKMG stacks is mainly supported by reports in Applied Physics Letters [33, 34], in Microelectronic Engineering [35] and Solid State Electronics [36]. The part on S/D regions is mostly covered in Solid State Electronics [37].
Chapter 4, “Devices”, reports on CMOS-compatible self-aligned InGaAs MOSFETs with evolving device architectures towards higher performances: bulk vs on-insulator, planar vs tri-gate, gate-first vs replacement-gate. Those devices are covered in reports at the International Electron Device Meeting [31], at the VLSI Technology Symposium [13, 32], at the European Solid-State Device Research Conference [38], at the Device Research Conference [39] and in Electron Device Letters [40].
Chapter 5, “Circuits”, demonstrates several implementations of hybrid InGaAs/SiGe CMOS circuits based on wafer bonding of blanket layers or local selective epitaxy, in 2D and in 3D configurations. Those developments are mainly reported at the International Electron Device Meeting [31, 41, 42]. Part of this work is also submitted for the VLSI Technology Symposium in 2016 [43].

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Substrates: InGaAs Integration on Si

Introduction

This chapter focuses on the material integration aspects of InGaAs on Si. The targets are to provide high-quality material on a Si platform, using processes which can be used in a manufacturing environment. The proposed solutions need to be cost-effective and take into account the process integration restrictions imposed by the large-scale fabrication of CMOS circuits. Two methods are proposed to integrate InGaAs either as blanket layers on large-scale substrates or as local micron-sized patches.
Firstly, direct wafer bonding (DWB) is explored in section 2.2 to fabricate InGaAs-on-insulator (InGaAs-OI) substrates on the same model as the industry-standard SOI substrates. The base layer transfer technology is developed and optimized to yield robust bonded interfaces and high thermal stability. A path towards large-scale manufacturing is demonstrated through the recycling of the donor wafers and the realization of 200 mm InGaAs-OI substrates. The fabrication of hybrid InGaAs/SiGe CMOS circuits is enabled by the proposed concept of dual-channel substrates.
Secondly, a local epitaxy technique in empty oxide cavities in proposed in section 2.3. It relies on the direct selective epitaxy of InGaAs on Si and yields micron-sized islands of InGaAs, where it is required in the CMOS circuit layout. This method is inherently compatible with the large-scale manufacturing requirements of the CMOS industry.
The material developments presented in this chapter are the basis for all InGaAs on Si device and circuit demonstrators reported in this thesis.

Direct Wafer Bonding

The development of DWB was pushed by the need of the microelectronic industry for SOI substrates. The concept is to bring the surface of a donor and of a target wafer into intimate contact in order to create a strong bond between the two substrates. The donor wafer is then submitted to some treatments in order to realize the transfer of an active layer from the donor wafer to the target wafer. During this treatment, the donor wafer might be preserved and re-used, or destroyed.
In the case of SOI substrates fabrication, the bonding between the two Si wafers is obtained through an oxide layer. SiO2 is grown or deposited on the surface of the target and/or donor wafer, the two surfaces are made hydrophilic through a wet clean process, and the wafers are bonded at room temperature. The bonding is obtained through the formation of H-bonds which are converted into Si-O bonds (through the release of some hydrogen or water at the interface) upon thermal treatment. Finally, part of the donor wafer is removed leaving a Si layer on top of the oxide layer (named buried oxide (BOX)) on the target Si wafer. The main challenges are the control of the final thickness, roughness and uniformity of the top Si layer as well as the removal of the donor wafer in a cost-efficient manner.
This technique became the industry-standard method for the fabrication of SOI sub-strates with the development of SmartCutTM[44]. It is a cost-efficient donor wafer release technique based on H-implantation, which provides an accurate control of the top Si thick-ness, roughness and uniformity without sacrificing the donor wafer: it can be recycled and serve for several subsequent bonding steps.
DWB is a very versatile technique that enables the integration of diverse materials on diverse substrates: strained SOI [45], hybrid orientation composite SOI [45], germanium-on-insulator [46], silicon on lattice engineered substrates [47], and many others.
The integration of III-V materials on insulator on Si by DWB has been an active field of research since the 1980’s mostly driven by optoelectronic applications. Its use for CMOS applications was introduced in [12] in 2009 with the demonstration of ultra-thin InGaAs-OI layers for the fabrication of n-MOSFETs. Inspired from this demonstration, the work presented in this thesis focused on several key aspects of the realization of ultra-thin body and BOX (UTBB) InGaAs-OI on Si substrates:
Thickness and roughness control of the transferred layer (section 2.2.1)
High thermal stability such that the InGaAs top layer can act as a virtual substrates for III-V epitaxy (section 2.2.2)
Figure 2.1: (a) Schematic process flow of the fabrication of UTBB InGaAs-OI substrates (1 to 5) and InGaAs regrowth module for S/D regions (6). (b) Picture of an InGaAs-OI substrate.
Recycling of the donor wafer (section 2.2.3)
Up-scaling path towards 300/450 mm substrates (section 2.2.4) Co-integration with ultra-thin SiGe layers (section 2.2.5)

Layer transfer of III-V heterostructures to Si wafers

The fabrication of an InGaAs-OI on Si wafer (described in Fig. 2.1) starts with a 2” semi-insulating high-grade (100)-oriented InP donor wafer loaded in a metal-organic va-por phase epitaxy (MOVPE) system. An etch-stop heterostructure composed of InGaAs, InAlAs and InP is grown at 550 C followed by the growth of the active layer of a cer-tain target channel thickness tch. The active layer can be either an InGaAs layer or an heterostructure composed of InGaAs, InAlAs and InP (to form quantum wells, top or bottom barriers, etc.). Subsequently, the donor wafer is loaded in an atomic layer deposi-tion (ALD) chamber where the BOX is deposited at temperatures ranging from 250 C to 300 C. ALD deposition is chosen for its low thermal budget, excellent thickness control and extremely low surface roughness.
The BOX is always deposited on the donor wafer so that the III-V/BOX interface can be engineered for low density of interface traps (Dit). For instance, an optimized MOS stack can be deposited at the InGaAs/BOX interface (from Chapter 3 section 3.2.3, used in Chapter 4 section 4.3.2), or a wider bandgap semiconductor barrier layer can be introduced (used in Chapter 4 section 4.2). Optionally, part of the BOX layer can also be deposited on the target Si wafer (see section 2.2.2). Figure 2.2: Ellipsometry thickness mapping of a 7 nm In0.53Ga0.47As active layer on a 10 nm BOX on Si after etch-stop removal.
The target 4” (100)-oriented n-type (n-type dopant density (Nd) = 1 1017 cm-3) Si wafer is wet cleaned for organic contaminants and its native oxide is stripped in diluted hydrofluoric acid (DHF). A thin and high quality native oxide is then chemically regrown by exposing the wafer to ozone-rich dionized water (DIO3), making its surface hydrophilic. The donor and target wafer surfaces are brought into intimate contact at room temper-ature and ambient atmosphere to initiate the bonding. The wafers are then annealed at 300 C for 2 hours in order to raise the bonding energy. The InP donor wafer is then etched in concentrated hydrochloric acid (HCl) until reaching the InGaAs/InAlAs etch-stop het-erostructure, which is etched in diluted acids to ensure a soft-landing on the active layer. It yields the final InGaAs-OI substrate.

Table of contents :

1 Introduction 
1.1 High-mobility materials for future CMOS nodes
1.2 Challenges and solutions to integrate InGaAs on Si
1.3 Requirements for self-aligned MOSFETs
1.4 Hybrid CMOS circuits
1.5 Thesis: Organization and relation to published work
2 Substrates: InGaAs Integration on Si 
2.1 Introduction
2.2 Direct Wafer Bonding
2.2.1 Layer transfer of III-V heterostructures to Si wafers
2.2.2 Thermal stability of InGaAs-OI layers and regrowth
2.2.3 Recycling of the donor wafer
2.2.4 Large-scale InGaAs-on-insulator substrates
2.2.5 Hybrid InGaAs/SiGe dual-channel substrates
2.3 Confined Epitaxial Lateral Overgrowth
2.3.1 Concept
2.3.2 Fabrication of empty cavities on Si refilled by III-V crystals
2.3.3 Material characterization
2.4 Conclusion and outlook
3 Process Modules: Gate Stack and S/D Regions 
3.1 Introduction
3.2 MOS Gate stack
3.2.1 a-Si based gate stack
3.2.2 Remote oxygen scavenging on high-k/InGaAs interfaces
3.2.3 Optimized plasma-based high-k/InGaAs gate stack
3.3 Contacts
3.3.1 Raised Source/Drain
3.3.2 Ni-InGaAs: Self-aligned silicide-like contacts
3.3.3 Direct metal contacts
3.4 Conclusion and Outlook
4 Devices: Self-aligned CMOS-compatible InGaAs MOSFETs 
4.1 Introduction
4.2 Gate-first Planar MOSFETs
4.2.1 Impact of Ni-InGaAs contacts on “bulk” devices
4.2.2 Split C-V and Effective mobility
4.2.3 Short-channel devices and roll-off characteristics
4.2.4 Tight-pitch InGaAs MOSFETs
4.3 Non-planar MOSFETs
4.3.1 Junction-less FinFETs
4.3.2 Replacement-gate FinFETs on Silicon
4.3.3 Gate-first FinFETs on selectively grown InGaAs on Silicon
4.4 Conclusion and Outlook
5 Circuits: Hybrid InGaAs/SiGe CMOS 
5.1 Introduction
5.2 2D Co-planar CMOS Technology
5.2.1 2D InGaAs/SiGe CMOS based on DWB
5.2.2 2D InGaAs/SiGe CMOS based on CELO
5.3 3D Monolithic CMOS technology
5.3.1 Circuit fabrication
5.3.2 Impact of nFETs fabrication on pFETs performance
5.3.3 InGaAs n-MOSFETs and 3D CMOS inverters
5.4 Conclusion and Outlook
6 Conclusion 
A List of Publications
B Contributions to this work
C Acknowledgements
D French Summary
D.1 Introduction
D.2 Substrats : Intégration d’InGaAs sur Si
D.3 Modules : Empilement de grille et régions S/D
D.4 Composants : Transistors auto-alignés compatibles CMOS à base d’InGaAs
D.5 Circuits : Technologie CMOS hybride InGaAs/SiGe
D.6 Conclusion
List of Figures
List of Tables
Bibliography

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