Impact of Metal-Oxide-Semiconductor gate stack properties on MOSFET device performance
The Metal-Oxide-Semiconductor Field Eﬀect Transistor (MOSFET) device is based on the field eﬀect mechanism . In physics, the field eﬀect refers to the modulation of the electrical conductivity of a material by the application of an external electric field. In MOSFETs, this field eﬀect is then related to the control of the semiconductor conductivity near its surface.
A MOSFET is a four-terminal device, but it can be seen as a combination of two orthogonal two-terminal devices, as shown in Fig. 1.1. The objective is to control the current flow between two ohmic contacts, the source and the drain, by the modulation of the charges in the semiconductor channel. Charge carriers in the semiconductor channel are controlled by two other terminals, the gate and the body or substrate, by capacitive coupling1. The threshold voltage (VTH) is the minimum gate-to-body voltage diﬀerence that is needed to create a conductive channel between the source and drain terminals. It is the conductive channel that allows the carriers to flow from the source to the drain.
The simplest MOS structure is the MOS capacitor and it is composed of a p-type or n-type doped silicon, a gate oxide and a layer of metal or polycrystalline silicon. By applying Kirchhoﬀ’s voltage law, the potential diﬀerence between the gate and the body terminals (VG) can therefore be decomposed as follows : VG = Φm Φsc + Vox + Vsc (1.1) where qΦm corresponds to the diﬀerence between the metal Fermi level and its vacuum level, qΦsc corresponds to the diﬀerence between the semiconductor Fermi level and its vacuum level, Vox is the drop voltage across the oxide and Vsc is the potential drop in the semiconductor.
The relationship between the charges in the semiconductor Qsc and the potential at the semiconductor surface (Vsc) can be described by the Poisson equation for electrostatics, according to classical electrodynamics . However, for ultra-thin oxide thicknesses and low field strengths, such interactions are better described by quantum Poisson-Schro¨dinger simulations (section 2.1.3). The charges induced in the semiconductor may be of three types : majority carriers, minority carriers and depletion charge. The type of charges can be controlled by the voltage applied to the gate, specifically by the Vsc. Indeed, the ability to induce and modulate a conducting sheet of minority carriers at the semiconductor/oxide interface is the basis of the operation of the MOSFET.
Let’s take the example of p-type semiconductor substrate. For an n-type semiconductor, the sign of Vsc has to be switched, as shown in Fig. 1.2.
• Vsc < 0 : Accumulation regime. Majority carriers are attracted to the surface of the semiconductor.
• 0 < Vsc < Φfi : Depletion regime. Majority carriers are pushed towards the bulk silicon, and so, their density decreases at the semiconductor/oxide interface. The only remaining charges are the thermally ionized dopant atoms at room temperature.
• Φfi < Vsc < 2Φfi : Weak inversion or subthreshold regime. Minority carriers density starts to increase, but charges are essentially the thermally ionized dopant atoms at room temperature. Transistor is in the « oﬀ » state or weak inversion under threshold voltage.
• 2Φfi < Vsc : Strong inversion regime. The transistor is in the « on » state. Minority carriers density becomes much more important than the doping concentration. The channel is formed between the source and the drain.
The heavily doped (n+ for NFETs and p+ for PFETs) source/drain regions, are used to make an ohmic contact with the conductive channel for |VG| > |VTH| so that a voltage diﬀerence between the source and the drain (VDS) will result in a current flow (IDS) of minority carriers (electrons for NFETs and holes for PFETs) from the positive voltage at the drain terminal to the negative voltage at the source. This current flow of minority carriers is also known as drive current and is one of the main MOSFET device performance parameters. In the « oﬀ » state, the drive current is very small (ideally zero) and in the « on » state, it is a function of both VG and VDS.
Metal-Oxide-Semiconductor gate stack properties
Gate dielectric capacitance and equivalent oxide thickness
The capacitance is the ability of a body to store an electrical charge. The most common form of energy storage device is the parallel plate capacitor, which consists of two electrical conductors (plates) separated by a dielectric (i.e. an electrical insulator that can be polarized by the application of an electric field). When a potential diﬀerence V is applied to the conductors, an electric field develops across the dielectric, causing positive charge (+Q) on one plate and negative charge (-Q) on the other plate. The capacitance C is defined as the ratio of charge on each conductor to the voltage V between them (C = Q/V).
In a Metal-Oxide-Semiconductor capacitor, one of the plates is the metal gate and the other, is the silicon substrate. However, in the MOS capacitor the applied voltage may be used to control the type of interface charge induced in the channel (majority carriers, minority carriers, and depletion charge). The dielectric consists of the gate oxide with a relative permittivity εox (commonly known as the dielectric constant) and thickness Tox. Consequently, the gate dielectric capacitance per unit area (Cox) can be expressed as follows : Cox = ε0εox (1.2) where ε0 = 8.854… x 10−12 F/m is the vacuum permittivity.
In order to quickly compare diﬀerent dielectric materials to the industry standard silicon oxide (SiO2) dielectric, a new definition has been proposed : Cox = ε0εSiO2 (1.3) where EOT (Equivalent Oxide Thickness) is defined as : EOT = Tox εSiO2 (1.4)
Both EOT and Cox are important gate stack properties that influence the performance parameters of MOSFET devices such as the drive current (IDS) and the threshold voltage (VTH), as will be detailed in section 1.1.3.
Flat band voltage
The gate bias (VG) always corresponds to the potential diﬀerence between the metal and semiconductor Fermi levels, EF,m and EF,sc, respectively. The energy band diagram of the MOS structure for VG = 0 is quite complex and shows band bending due to the semiconductor and metal work function diﬀerence. The flat band voltage (Vfb) is a special bias condition which corresponds to the gate bias with no charge in the substrate. In other words, Vfb is the bias condition leading to no band bending at the substrate interface. It corresponds to Qsc = 0, and for constant doping level in semiconductor, it usually leads to Vsc = 0. However, at flat band condition, the term Vox is not necessarily zero  . Indeed, it is influenced by oxide stack charges density and interfacial voltage drops . The flat band expression can thus be deduced from Eq. 1.1 Vfb = Φm Φsc + Vox (1.5)
Considering a p-type substrate and an bilayer high-κ/SiO2 oxide stack with no oxide charges at all, the energy band diagram of the MOS structure at flat band condition is described in Fig. 1.3a. E0, EC , and EV are the energy of vacuum level, the energy of the bottom of the conduction band, and the energy of the top of the valence band of silicon, respectively.
a) without any oxide charge and b) with charges in the oxide and dipoles at high-κ interfaces.
However, Vfb for real devices is a process-dependent parameter and its control is currently one of the most serious problems, especially in bilayer high-κ/SiOx oxide structures, currently used in 14 nm FDSOI technology and other modern MOSFET technologies. Gate stack charges density and interfacial voltage drops due to the formation of an electrostatic dipole (δ) at both high-κ interfaces have been reported as the origins of the Vfb shift. An energy band diagram for such non-ideal MOS structure at flat band condition is shown in Fig. 1.3b . Note that the vacuum level is influenced by the presence of charges and interfacial drops. As a result, processes variations lead to an eﬀective work function (WFeﬀ) diﬀerent from Φm. The eﬀective work function is of first interest, since it drives VTH. In the next sections, we first describe the gate stack charges and the interface electrostatic dipole and their impact on Vfb. Next, the expression of WFeﬀ in the case of a bilayer high-κ/SiOx oxide structure will be defined, as well as the considerations assumed and validated to simplify the WFeﬀ expression in this thesis work.
Gate stack charges density and its impact on flat band voltage
In real MOSFET devices, four general types of charges can be identified and associated to the Si/SiO2 system   : bulk or interfacial fixed charges (Qf ), mobile ionic charges (Qm), interface trapped charges (Qit), and oxide trapped charges (Qot). The origin of these charges has been related to some impurities or defects incorporated into the oxide during oxide growth or subsequent fabrication process steps.
The mobile ionic charges (Qm) are primarily due to positive alkali ions in the oxide such as Na+, K+ and Li+ , incorporated during device processing steps. These impurities cause reliability problems under high temperature and high voltage operations as they can migrate from an interface to another.
The oxide trapped charges (Qot) may be positive or negative due to holes or electrons trapped in the bulk of the oxide. Trapping may result from ionizing radiation, avalanche injection, or other similar processes. Unlike fixed charge, oxide trapped charge is generally annealed out by low temperature (< 500 ◦C) treatment, although neutral traps may remain .
The fixed oxide charges (Qf ) are positive or negative charges located in the dielectric or at Si/SiOx interface. In a bilayer high-κ/SiOx oxide structure, fixed charges can be located at: a) bulk high-κ layer, b) high-κ/SiOx interface, c) bulk SiOx layer, d) SiOx/Si interface, and e) metal/high-κ layer . We name QSi/SiOX the sheet of charges at SiOx/Si interface and QSiOX/HK the sheet of charges at high-κ/SiO2 interface. Fixed oxide charges do not move and exchange charge with the underlying silicon. They also do not change with the applied voltage .
The interface trapped charges (Qit) are positive or negative charges located at the Si/SiOx interface. They are due to structural, oxidation-induced defects, radiation-induced defects or other dangling bonds at this interface. Unlike fixed charge or trapped charge, interface trapped charge is in electrical communication with the underlying silicon and can thus be charged or discharged, depending on the surface potential Vsc. Most of the interface trapped charges can be neutralized by low temperature (450 ◦C) hydrogen annealing or forming gas annealing .
The eﬀect of each charge on the Vfb condition depends on its distance from the oxide/semiconductor interface and can be calculated from Gauss Law. This is why it is convenient to separate the charges between bulk charges and interface charges. From Gauss Law application, we can deduce the Vfb shift induced by each type of oxide charge: ΔVfbbulk, ΔVfbf, and ΔVfbit for bulk charges, interface fixed charges, and interface trapped charges, respectively. Bulk charges include the mobile ionic charges, the oxide trapped charges and the bulk fixed charges and their impact on flat band voltage is given by: 1 Z TOX ρ(z) Z z du where ρ(z) is the gate dielectric charge distribution per unit volume. For a constant bulk charge density in a dielectric layer, the voltage drop will then vary with the square of its thickness. Interface fixed charges for a bilayer high-κ/SiOx oxide structure can be expressed as follows: f QSi/SiOX EOT QSiOX/HK EOTHK (1.7)
A sheet of charges at the high-κ/SiOx interface or at SiOx/Si interface induces a voltage drop which increases linearly with the distance from the gate. Finally, interface trapped charges located at the Si/SiOx interface influences the Vfb as follows: ΔVfbit = Qit(Vsc) EOT (1.8)
It is therefore evident that the presence of charges in the oxide changes Vfb. As the threshold voltage is related to the Vfb, charges also directly influence the threshold voltage and most of the performance parameters of MOSFET devices, which will be described in section 1.1.3. Even worst, charges aﬀect not only threshold voltages but also eﬀective mobilities, and device stability in MOS devices, and also junction leakage, noise, and breakdown voltage in discrete transistors and digital integrated circuits. In addition, defects are undesirable for four reasons. Firstly, charges trapped in defects shift the gate threshold voltage of the transistor. Secondly, the trapped charge changes with time so VTH shifts with time, leading to instability of operating characteristics. Thirdly, trapped charge scatters carriers in the channel and lowers the carrier mobility. Fourthly, defects are the starting point for electrical failure and oxide breakdown , and then they cause unreliability.
Table of contents :
1 Gate stack technology for 14 nm FDSOI MOSFET devices
1.1 Impact of Metal-Oxide-Semiconductor gate stack properties on MOSFET device performance
1.1.1 MOSFET operation
1.1.2 Metal-Oxide-Semiconductor gate stack properties
1.1.3 MOSFET performance parameters influenced by the gate stack
1.2 Gate stack fabrication process
1.2.1 Oxidation methods and Gate dielectrics
1.2.2 Metal gate electrode and deposition techniques
22.214.171.124 Thin metal gate films deposition techniques
126.96.36.199 Deposition of ultra-thin Titanium nitride films and Aluminum and Lanthanum monolayers by RF-PVD magnetron sputtering
1.3 Metal gate integration in 14 nm Fully-Depleted SOI devices
1.3.1 FDSOI architecture
188.8.131.52 Multi-VTH offer
184.108.40.206 Effective work function requirements for Fully-Depleted SOI devices
1.3.2 Sacrificial metal gate-first process integration
1.3.3 Random local VTH fluctuations
2 Process flow and test methodology for electrical and physicochemical characterization of gate stack
2.1 Techniques of electrical characterization
2.1.1 Test structures
220.127.116.11 Hybrid devices
18.104.22.168 Short channel test structures
22.214.171.124 Matching test structures
2.1.2 Process flow simplification for nominal devices and specific research wafers
126.96.36.199 Nominal devices
188.8.131.52 Devices with beveled oxide
2.1.3 Measurements and electrical parameters extraction
184.108.40.206 Experimental set up for C-V measurements
220.127.116.11 Extraction of electrical parameters from C-V characteristics
2.2 Physicochemical characterization
2.2.1 Four-point probe resistance measurement
2.2.2 X-Ray Fluorescence
18.104.22.168 Advantages and limitations
22.214.171.124 Methodology for the characterization of the diffusion of gate additives
2.2.3 Secondary Ion Mass Spectrometry
2.2.4 X-Ray Diffraction
3 Effective work function modulation by accurate control of diffusion of sacrificial lanthanum and aluminum into gate stack of high-! based NFET devices
3.1 State of the art of lanthanum in gate stack
3.1.1 Lanthanum oxide as alternate gate dielectrics
3.1.2 Lanthanum incorporation into Hf-based dielectrics
3.1.3 Lanthanum incorporation into TiN
3.2 Effective work function modulation by accurate control of sacrificial lanthanum diffusion
3.2.1 Device fabrication and electrical characterization
3.2.2 Diffusion characterization by X-Ray Fluorescence
3.2.3 Influence of high-! dielectrics on the effective work function shift induced by lanthanum incorporation
3.3 State of the art of aluminum in gate stack
3.3.1 Aluminum oxide as alternative gate dielectrics
3.3.2 Aluminum incorporation into Hf-based gate dielectrics
3.3.3 Aluminum addition into TiN
3.4 Effective work function modulation by accurate control of sacrificial aluminum diffusion
3.4.1 Device fabrication and electrical characterization
3.4.2 Diffusion characterization by X-Ray Spectroscopy
3.4.3 Influence of high-! dielectrics on the effective work function shift induced by aluminum incorporation
3.5 Sacrificial vs standard final approach
4 Role of TiNon effective work function andmatching of 14 nm FDSOI devices
4.1 State of the art of the modification of the effective work function induced by the TiN
4.1.1 Modulation of the effective work function by tuning TiN thickness
4.1.2 Modulation of the effective work function by tuning N composition in TiN gate
4.1.3 Effect of the oxygen incorporation in TiN gate on the effective work function
4.1.4 Effect of the reduction of oxygen vacancy defects on effective work function
4.2 Characterization of the impact of TiN on the effective work function of 14 nm FDSOI devices
4.2.1 Impact of nitrogen content into TiN on the effective work function
4.2.2 Influence of high-! dielectrics on the work function shift induced by TiN thickness
4.2.3 Titanium and nitrogen diffusion into HfSiON/SiON and HfON/SiON stacks
4.2.4 Influence of Arsenic doping into Poly-Si layer on the effective work function
4.3 Impact of deposition process on TiN microstructure and local VTH variability
4.3.1 Impact of pressure conditions on microstructure of TiN deposited by RF-PVD
4.3.2 Impact of RF power conditions on microstructure of TiN deposited by RF-PVD
4.3.3 Electrical impact and local VTH variability improvement with TiN microstructure engineering
4.3.4 TiN microstructure versus thickness
Conclusions and Perspectives