High-Speed Reconfigurable Signal Processing

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Chapter 2 Background

A high-speed yet configurable processor is needed for a high data rate software-defined radio (SDR) such as an ultra-wideband SDR. This chapter discusses previous efforts in research areas pertaining to this work, including high-speed reconfigurable signal processing, software-defined radio, and ultra-wideband communications. An overview of ultra-wideband technology and modulation schemes is also presented.

High-Speed Reconfigurable Signal Processing

The need for high-speed yet configurable digital signal processing has been addressed by researchers in the past. Some have  hosen to use fine-grained, commercial off-the-shelf (COTS) FPGAs, while others have chosen to implement custom, coarse-grained architectures. One project that took the latter approach was the Dynamically Reconfigurable Architecture for Mobile Systems (DReaM). The DReaM architecture was an effort to target signal processing for mobile systems with a coarse-grained, domain-specific approach [7]. DReaM combined configurable routing with 8-bit integer operators, dual-ported RAMs, and Spreading Data Path (SDP) units to implement radio functionality. The SDP was used to perform communication-specific tasks such as CDMA-based spreading or complex correlation used in QPSK modulation. One application for the DReaM architecture was a CDMA RAKE receiver that was able to accommodate a symbol rate of 32 M-symbols/s.Another architecture that uses a custom coarse-grained architecture is detailed in [8].This system combined a custom reconfigurable parallel processor with a DSP and an FPGA for configurable routing. The custom processor was the XPP-64A, which implemented an array of ALU Processing Array Elements (ALU-PAEs). The ALU-PAEs implemented a DSP-based instruction set that operated on 24-bit words. The ALE-PAEs also included dual-ported RAM and configurable routing. This architecture was targeted to a RAKE receiver and an OFDM decoder.Other systems such as the Berkeley Emulation Engine (BEE) and BEE2 have exploited the ability of FPGAs to quickly process large amounts of data in parallel. The BEE and BEE2 platforms were designed to offer massively parallel processing of data with an emphasis on hardware emulation [9, 10]. The original BEE system was comprised of BEE Processing Units (BPUs), each of which contained 20 Xilinx Virtex-E FPGAs. Sixteen FPGAs in each BPU were used for computation and the remaining four were used as configurable crossbar switches. Tool flows using Simulink and Xilinx System Generator allowed for emulation of ASIC designs with a high level of design abstraction. One test of the BEE system was an emulation of a TDMA receiver with a 806 kHz symbol rate. This design used three processing FPGAs and one crossbar FPGA and was able to operate at a maximum frequency of 25.0 MHz [9]. A single-channel 2.4 GHz radio system tested on the BEE platform was able to operate in real-time with a 32 MHz system clock rate [11].The BEE2 platform expanded on the BEE concept and took advantage of newer technologies. Each BEE2 compute module contained five Xilinx Virtex-II Pro FPGAs. Each FPGA was connected to four 400 MHz DDR DRAM DIMMs, giving up to 4 GB of memory per FPGA with a memory bandwidth of up to 12.8 Gbps. In each module, four FPGAs were used for computation, and one was used for control. The control FPGA had additional con-nectors for off-board communication. The FPGAs were connected together on-board with parallel LVCMOS connections and could communicate to off-board entities with high-speed serial transceivers. BEE2 was designed not only for emulation but also for implementation of high-speed DSP applications. One use of the BEE2 system was a cognitive radio test bed [12]. BEE2 performed signal processing functions for the test bed. In another application, the BEE2 processed 16 Gbps of digital data to implement a spectrometer with sub-hertz spectral resolution over 800 MHz.While BEE2 has been shown to be useful in circuit emulation and in signal processing,there exists a drawback to using such a general computation engine. Because BEE2 was designed to use high-speed serial links for off-board communications, complex front-end boards were needed to interface with BEE2. In [12], the front end board contained a Xilinx Virtex-II Pro FPGA in addition to the analog filters, the ADC, and the DAC. The FPGA was needed for communication with the BEE2 board. A more application-specific processing system could use the FPGA connected to the ADC and DAC as the processing element,instead of offloading the processing to another system.


1 Introduction
1.1 Motivation
1.2 Contributions 
1.3 Thesis Organization 
2 Background 
2.1 High-Speed Reconfigurable Signal Processing 
2.2 Software-Defined Radio 
2.3 Ultra-Wideband Communications
2.3.1 Impulse Ultra-Wideband Signals
2.3.2 Impulse Ultra-Wideband Modulation Schemes
2.3.3 FCC Regulations
2.4 Summary 
3 Ultra-Wideband Transceiver System 
3.1 Time-Interleaved Sampling
3.2 Analog to Digital Converters 
3.3 ADC Data Bus Timing Budget 
3.4 Field-Programmable Gate Array 
3.5 RF Front End
3.6 Prototype Board
3.7 Final Radio Receiver Board
3.8 Transmitter Board 
4 FPGA Subsystem Design
4.1 ADC Data Capture 
4.2 Processor System Architecture 
4.3 Clock Uncertainty and Synchronization
4.3.1 FPGA Clock Uncertainty
4.3.2 ADC Reset Uncertainty
4.4 Pilot-Based Matched Filtering Receiver
4.4.1 Acquisition
Coarse Acquisition
Fine Acquisition
4.4.2 Pilot Pulse Reception
4.4.3 Data Demodulation
Partial Correlation Unit
Schedule and Coefficient Generation
Adder Tree and Comparator
4.4.4 Real-Time Tracking
4.5 Vital Signs Monitor
5 Results 
5.1 Initial System Testing 
5.2 Data Capture 
5.3 ADC Reset Testing
5.4 Transmitter Board
5.5 Pilot-Based Matched Filter Receiver 
5.6 Vital Signs Monitor
6 Conclusion 
6.1 Future Work 



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