Metal-Oxide-Semiconductor Capacitor operation regimes

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3D integration technologies overview

Despite the development of new device architectures, capable of overcoming scaling issues, Moore’s law is running out of steam and a potential end is envisioned. The latter is mainly because the feature size of the devices is approaching the fundamental limit of an atom. The foreseeable reach of Moore’s Law limits, the increased needs in terms of performance, space saving and low power consumption as well as the growing menace of RC delay in recent times led in the 80’s to the concept of integrating functionalities in three-dimensional modules [11]–[17]. These constitute a System in Package (SiP) combining conventional digital technologies (processor, memory controller, graphics solution, inputs / outputs, network connections, microsystems electromechanical) fabricated in different processes.
Conventional planar integration can be considered as two-dimensional. Thus, three-dimensional integration refers to the stacking of integrated circuit layers, interconnected vertically. The dominant approaches for three-dimensional integration in a single package can be encapsulated in 2 categories: parallel and sequential. The former term is referring to a method where the two wafers are processed separately and stacked -and contacted- afterwards (Fig. 1.2 (a)). In that case the alignment is made during the bonding and its 3-σ error is nowadays around 200nm [18]. In brief, the 3-σ error accounts for nearly 100% of the total alignment variation and is determined by calculating the standard deviation of the normal (Gaussian) distribution of the variation and multiplying it by three. There are several types of wafer bonding, the most prominent ones being copper-to-copper (Cu-to-Cu) and Hybrid bonding and Through-Silicon Via (TSV).
On the contrary, 3D sequential integration technology (3DSI – also named 3D monolithic integration or 3D VLSI) refers to the vertical stacking of active devices that are processed sequentially, i.e. each tier of devices is processed over a pre-patterned one (Fig. 1.2 (b)). This imposes that the alignment is made by lithography and the 3-σ error is around 5nm for a 28nm node [19]. Consequently, 3DSI can offer the highest density of vertical interconnects (>5×106 3D via/mm2 in [20] and up to 108 3D via/mm2 in [19], [21]), when compared to the other alternatives [22], [23], as shown.
There are multiple levels of partitioning a circuit following a three-dimensional integration: core-level, block-level, gate-level and ultimately transistor-level partitioning (Fig. 1.4). The latter, being the last one in the granularity scale can be realized exclusively with 3DSI. Furthermore, 3DSI is the only 3D technology to enable partitioning with all granularity scales.
3DSI offers plenty of opportunities. Traditionally, the main virtue resulting from three-dimensional integration has been on the “More Moore” direction, attributed to the drastic decrease in the length of interconnects in an integrated circuit. Indeed, as shown in Fig. 1.5, assuming a planar integrated circuit with an area A, the longest interconnect (i.e., the line between the points X and Y) has a length Lmax = 2√ . Partitioning the same circuitry in two layers, each having an area of A/2, the length of the longest interconnect is now Lmax = √2 .
Following the same logic, increasing the number of layers to four, the area of each die is further reduced to A/4, and the longest interconnect would have a length of Lmax = √ . By this simplified example it can be seen that there is a significant reduction of the wiring length and consequently the interconnection RC delay, leading to considerable advantages over conventional planar integration. Specifically, it has been reported that for a two-tier 3DSI there is 50% area reduction, 20% power limitation and 26% performance boost owing to the interconnect length reduction [24], [25]. Consequently, 3DSI has been envisioned as an alternative to the dimensional scaling of devices which is reaching its limits.
Nowadays, the versatility of applications that can be integrated in each sequential tier is emphasized towards the “More than Moore” direction. The latter enables the possibility to integrate heterogeneous complex systems with a large number of functionalities in a reduced form factor, while increasing the circuit performance (in terms of enhanced bandwidth and reduced power consumption) as shown in Fig. 1.6.
A highly anticipated application within the More than Moore approach is the smart sensors which embed the sensor interface with all the processing and memory elements stacked on top of it. In this manner, applications fabricated in different technologies that are connected with low-latency vertical interconnections, enable the acceleration of the signal processing in a reduced form factor. An example of that is the smart imager that incorporates pixels with stacked analog and digital processing units as illustrated in Fig. 1.7.
Although 3D stacking technologies are widely used for 3D CIS [28], [29], constraints of traditional 3D stacking alignment capabilities forbid the more aggressive pixel miniaturization required for future generations of CIS [30], [31]. The feasibility of Back-Illuminated CIS with miniaturized pixels realized in 3DSI has been investigated in [31], where a 44% increased photodiode area for 1.4μm pitch was reported owing to the 3D partitioning at the pixel level. Moreover, 3DSI is the dominant pathway for pixel partitioning with pitch in the 1 μm range [32].

Electrical measurement and analysis methods

For the purpose of this study, electrical measurements were performed on 3D sequentially integrated wafers, processed with the CoolCubeTM technology in CEA-LETI (Fig. 1.8).
The simulation study was conducted with the aid of leading EDA tools. For the electrostatic coupling analysis, numerical simulations were performed using Silvaco ATLAS [33], a generic TCAD tool for physically-based two (2D) and three-dimensional (3D) simulation of semiconductor devices. Additionaly, Silvaco CLEVER [34] was used to extract the parasitic capacitances within the monolithic 3D structures. This tool is a field solver, intended for complex arbitrary structures where layout effects dominate, providing accurate results in a sufficient amount of time.
Due to the small electrical size of the structures simulated (i.e., the ratio between the largest distance between two points in the structure divided by the wavelength of the electromagnetic fields) being in the range up to 1/10, quasi-static formulations have been used to carry out this study. By using this approximation, the wave propagation delays are small enough to be neglected. Hence, even for frequencies up to the GHz regime, quasi-static tools provide accurate description of the coupling fields without the need of dedicated high frequency simulations. Therefore, the above-mentioned simulation tools are adequate for an accurate analysis particularly in the low-frequency domain. Yet, Ansys HFSS (High Frequency Electromagnetic Field Simulation) [35], a full-wave EM simulator that predicts non-quasistatic effects, has been utilized for the validation of the TCAD simulations in the high-frequency domain.
Lastly, the circuit simulations were performed within the Cadence Virtuoso Platform [36] using a parametrized version of the Leti-UTSOI model [37]. The proper parametrization of the model was employed to reproduce the experimental behavior and also to include the electrostatic coupling via the Back Gate (BG) of the transistor model.

Challenges & Motivation

The primary and main challenge of Monolithic 3D integration is associated with the fabrication of the top active layer (or layers) in such manner to preserve the electrical characteristics of the bottom one. Therefore, there is a temperature barrier (Thermal Budget (TB)) in order to avoid the degradation of the bottom tier’s device, therefore the classical processing steps for the top tier’s device fabrication are forbidden. To cope deal with this obstacle, the TB of the top devices is kept below 500°C to preserve the bottom FET from any degradation [19], [21].
Fig. 1.9 TEM cross-section of two stacked transistors fabricated in 3DSI.
Furthermore, the different tiers are linked with 3D contacts, as shown in Fig. 1.10, which has limits in its aspect ratio (AR). This type of contact is a conventional one (Tungsten plug in oxide), however it has a greater height, predominantly defined by the ILD thickness (illustrated in Fig. 1.9). The AR of the 3D contact is expressed as 3 = 3 (1-1) where W3DCO is the width of the 3D contact which scales with the stacked device technology and H3DCO is its height. Due to limits imposed by etching, the shape of a standard and 3D contacts is a trapezoid, thus a high AR reduces its bottom-end area. This by turn limits the maximum allowed current density, hence the lowest possible AR is preferable. An AR close to the one of standard contact, is required nowadays in terms of processing, hence the solution to achieve that is to keep the ILD thickness below 350nm.
Another significant challenge of this technology, which is also the topic of this thesis, is the danger of electromagnetic interference between the sequential tiers. As explained previously, the ILD separating the top-tier device from the bottom one is very thin (few hundreds of nm), so that a good 3D contact AR is preserved. Therefore, the ILD can become a pathway for DC and electromagnetic coupling between adjacent tiers, limiting their performance as a result, or shifting the circuit’s operating point.

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State-of-the-art studies on electromagnetic coupling in 3D technologies

The design of systems in a single chip is one of the current obstacles in the semiconductor industry. Numerous compatibility issues in terms of materials, process integration and functionality, emerge in this contemporary scheme. Over and above, associating circuits of different nature, functioning and operating frequency range within the same chip, and more importantly placed at close distances, is a major challenge.
It is well known from conventional planar integration that the design of circuits operating within a highly noisy environment is extremely critical and presents many challenges. To minimize the noise impact on the sensitive active parts of a circuit, the solutions often consist in oversizing the critical distances between the functional blocks. However, these solutions limit the benefits of the technological advances (form factor and interconnection delay reduction). For these reasons, the characterization and modeling of noise coupling is of increasing interest.
In the general context of 3D integration, numerous studied have been reported regarding the electromagnetic interference between sensitive parts of the chip, however the majority of them concerns parallel integration. In particular, TSV to active device coupling has been extensively characterized [38]–[41] and modeled [42]–[47] whereas its impact on the device and circuit performance has been in-depth analyzed in several studies [41]–[44], [46], [48]–[50].
On the other hand, to date there is poor amount of literature concerning coupling between the different tiers and particularly active devices in sequential 3D integration. Electrostatic coupling effects in 3DSI have been already presented in principle [51]–[56] and experimentally verified [57], whereas performance analysis taking into account the impact of electrostatic coupling has been performed in [52], [55], [58]–[61]. However, these studies cannot provide significant conclusions about the critical dimensioning of the stacked devices. Moreover, they consider homogeneous integration (specifically the tiers are comprised exclusively of digital circuits) and more importantly they partition the circuit in different tiers of 3DSI.
Several modeling considerations have been reported in [44], [62] concerning capacitive coupling in TOV technology. This process scheme is similar to 3DSI since it refers to stacked SOI devices separated by an oxide medium with Through-Oxide-Vias (TOVs) being the vertical contacts. The models reported evaluate the coupling capacitances formed between TOVs and active devices placed at the upper tiers, however they cannot evaluate the coupling impact between stacked devices. Nonetheless, although some modeling considerations are reported in [59]–[61] for the coupling between active devices in monolithic logic circuits, these models rely mainly on parasitic extraction and don’t predict the impact of arbitrary geometric configurations and scaling of the devices (layout effects).
Lastly, solutions to coupling effects in 3DSI have also been considered in [63], [64], where the inter-tier shielding methods are investigated. Additionally, [64] experimentally presents their technological achievement on a buried metal line, functioning as a shielding layer between two tiers of a 3DSI scheme.

Main contributions and thesis outline

This thesis aims to provide a deep understanding of the underlying physical mechanisms responsible for the electromagnetic coupling between the different tiers in 3DSI as well as a complete study how these coupling effects may impact a circuit’s operation. For the latter, a comparative study among planar and 3DSI has been performed. The most critical cases of digital, analog and mixed-signal/RF circuit designs have been examined, in order to draw a reliable conclusion for every case. Lastly, several techniques to mitigate the impact of coupling effects are suggested for the most sensitive circuits, targeting an efficient process flow, compatible with sequential 3D as well as convenient rules for the design of monolithic 3D circuits.

Table of contents :

Abbreviations
1.1 A brief historical review of CMOS technology
1.2 3D integration technologies overview
1.3 Electrical measurement and analysis methods
1.4 Challenges & Motivation
1.5 State-of-the-art studies on electromagnetic coupling in 3D technologies
1.6 Main contributions and thesis outline
2.1 The MOSFET transistor
2.1.1 Metal-Oxide-Semiconductor Capacitor operation regimes
2.1.2 Definition of MOSFET electrical parameters
2.1.3 Body effect
2.1.4 Short-channel effects
2.2 The FD-SOI device architecture
2.2.1 SOI substrate technology
2.2.2 FDSOI device geometry
2.2.3 Front/Back interface charge coupling
2.3 Electromagnetic coupling and transfer of energy between electrical components
2.4 Noise sources in devices and circuits
2.4.1 Intrinsic noise sources
2.4.2 Extrinsic noise sources
2.4.3 Noise coupling in circuits
2.5 Conclusion
3.1 3D sequential structure description
3.1.1 Mixed-signal opportunities by the use of 3DSI
3.1.2 3DSI process flow for digital devices
3.1.3 Characteristic dimensions and performance of 3DSI devices under test
3.1.4 Structure layout of 3DSI devices under test
3.2 Impact of DC coupling on top/bottom device performance
3.2.1 Experimental results
3.2.2 Simulation results
3.2.3 Impact of static coupling on the performance of top-tier digital devices (VDD=1V)
3.2.4 Impact of static coupling on the performance of top-tier analog devices (VDD=2.5V)
3.3 Impact of AC coupling on top/bottom device performance
3.3.1 Small-signal analysis
3.3.2 Transient response of top-tier devices to bottom-tier device aggressor signals
3.3.3 Inter-tier versus intra-tier coupling
3.4 Conclusion
4.1 Impact of inter-tier coupling on circuit operation
4.1.1 2-bitcell Sequential 3D SRAM (Digital on Digital case)
4.1.2 RO stacked on top of an analog tier (Mixed-Signal/RF on Analog case)
4.1.3 RO stacked on top of a digital tier (Mixed-Signal/RF on Digital case)
4.2 Methods and techniques to mitigate inter-tier coupling effects in 3DSI
4.2.1 Critical dimensioning of 3DSI structures and 3D design rules
4.2.2 Inter-tier shielding through GP: challenges and solutions
4.3 Conclusion
5.1 Introduction
5.2 Principles and operation of a CMOS imager
5.2.1 CIS standard architectures
5.2.2 Pixel metrics
5.2.3 Pixel noise parameters
5.2.4 Process integration optimization
5.3 Inter-tier Coupling at Device Level
5.3.1 Simulation Setup
5.3.2 Impact on electrical parameters
5.4 Inter-tier Coupling at Pixel Level
5.4.1 Read-out circuit block and pixel metrics
5.4.2 Impact of TG coupling on pixel electrical parameters
5.4.3 Inter-tier GP necessity
5.5 Conclusion
6.1 Parasitic extraction of lumped coupling elements in 3DSI
6.1.1 Definition of coupling capacitances in 3DSI
6.1.2 Effect of 3D contacts on coupling capacitances
6.2 Coupling-induced VTH shift modeling for stacked devices
6.2.1 Charge-coupling factor expression for long-channel top-tier devices
6.1.1 Modeling the effective ILD capacitance of stacked devices (CILD,eff)
6.3 Inter-tier dynamic coupling effects modeling
6.4 Inter-tier GP shielding modeling
6.4.1 DC modeling of inter-tier GP – Impact on coupling induced ΔVTH of the stacked devices
6.4.2 AC modeling of inter-tier GP
6.5 Conclusion
BIBLIOGRAPHY

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