New method for the extraction of the threshold voltage and current gain factor mismatch and new drain current mismatch model
This methodology chapter proposes a new Y-function based method for the extraction of the threshold voltage (Vt) and current gain factor (β) mismatch. A drain current mismatch model is also proposed that takes into account the value and variability of Rsd.
This chapter is divided into the following five sections.
o Section I discusses the need to revise the drain current mismatch models by considering the influence of the values and variability of Rsd in advanced technologies.
o Section II details a proposed Vt and β mismatch extraction method based on the Y-function statistical variability study. The method is shown to overcome the influence of Rsd values.
o Section III demonstrates a simple drain current mismatch model valid in strong inversion regime that includes the contributions of Vt, β and Rsd values and mismatch.
o Section IV presents the experimental results. The new extraction method and the new drain current mismatch model were applied to 28nm FDSOI and Bulk devices of different dimensions and conclusions are discussed.
o Section V closes the chapter with general conclusions and perspectives.
Introduction and motivation of this work
The drain current mismatch is one of the critical problems in scaled MOSFET‟s. Since the beginning of variability studies it has been analyzed that the local fluctuations of the threshold voltage (Vt) and current gain factor (β) are the major sources of drain current (ID) mismatch [Lakshmikumar86] [Croon 02a].
As the channel length is scaled down, the source/drain series resistance (Rsd) becomes a non-negligible contribution to the total device resistance (Rtot). Figure II. 1.a shows that for long-gate transistors Rsd is negligible compared to the channel resistance (Rch). However, when the gate length is reduced, Rsd is not any more negligible compared to Rch, and the total device resistance will be equal to Rch + Rsd as shown in Figure II. 1.b.
This Rsd contribution to the total device resistance has been demonstrated to limit the drain current performance of advanced MOSFET‟s [Ng 87] & [Thompson 98]. Figure II. 2 shows that, in strong inversion regime and in the linear region, the drain current decreases when Rsd is increased.
Typical values are assigned to the parameters to plot the Rsd contribution: L=0.05μm/W=0.08μm and Rsd=0 and Rsd=2775Ω and drain voltage VD=50mV.
Moreover, in regards to mismatch issues, Markov showed in [Markov 11] & [Markov 12] that for short channel lengths, the local fluctuations of Rsd represent an additional contribution to the drain current mismatch. This phenomenon is more pronounced in ultra-thin silicon body Fully Depleted Silicon On Insulator (FDSOI) devices.
Finally, Rsd has an important impact on the ID values, and its variability has been demonstrated in literature to have an impact on the drain current mismatch. Any future drain current mismatch model for advanced technologies must therefore take into account this contribution.
New Y-function based mismatch extraction method (strong inversion regime)
The main contributions to the drain current mismatch reported in literature are the threshold voltage and the current gain factor [Lakshmikumar86] [Croon 02a]. Moreover, different techniques and methods to extract the Vt and β values have also been reported, as detailed in section I.2.
One of these methods is the Y-function extraction technique, that allows the extraction of the values of Vt and β by excluding the Rsd contribution (section I.2.3). In this section a mismatch study was presented where the values of Vt and β were extracted for N samples of MOSFET transistor pairs. After applying a recursive filter to eliminate erroneous data, the standard deviation Vt and / of the Gaussian distribution was calculated (Section I.5).
In this paragraph, however, we propose a direct Vt and / extraction method, also based on the Y-function extraction technique, that avoids following the previously detailed Vt and β extraction steps. As shown in section I.3.3 and Figure II. 3, the Y-function has the advantage to be independent from Rsd.
The benefit of this new extraction method lies in its easy and rapid application, and in its independence from the values and variability of Rsd. The classical Y-function extraction method requires the extraction of Vt and β, followed by the calculation of their mismatch.
However, the new Y function mismatch extraction technique proposed in this paragraph (equation II.10) enables a direct extraction of Vt and β mismatches by simply considering the standard deviation of the Y function in strong inversion regime. Note that to maintain robustness with respect to the θ2 parameter while using this method, VG should not be very high (VGmax = 1V for this study).
New drain current mismatch model
Different models have been proposed to explain the behavior of ID mismatch: in weak inversion region [Forti 94], in weak to strong inversion regime as a function of gate bias and transistor geometry [Serrano 03], and in weak to strong inversion regime and in linear to saturation regime for transistors with pockets [Mezzomo 10a]. A mismatch model has been published by Croon [Croon 02a] that expresses the drain current mismatch as a function of the threshold voltage and current gain factor mismatch, the surface roughness scattering and the saturation velocity. This model gives mismatch trends as a function of the gate bias and of transistor geometries.
As shown in section II.1, Rsd has an important impact on ID. We therefore propose a new drain current mismatch model that takes into account the influence and variability of Rsd.
Starting from the first order Taylor approximation of the drain current, the principal contributions to ID variability are, based on literature, Vt, β and Rsd. The drain current derivative can be written as shown in Equation II.11.
Validation of the new drain current mismatch model
In order to validate the new drain current mismatch model in Equation II.19, the same short channel FD SOI transistor as section II.2 is considered with W=0.08μm and L =0.05μm.
The three models below are plotted as a function of VG in Figure II. 5:
a- Theoretical drain current mismatch represented by Equation II.12. Note that in Equation II.12 the difference between two identical MOS devices are used: σΔVt=0.01V, σΔβ/β =0.131 and σΔRsd =0.1Rsd
b- Drain current mismatch model represented by Equation II.19
c- Croon‟s model [Croon 02a] expressed in Equation II.20 (where Vt-β correlation, surface roughness scattering and saturation velocity have been neglected).
Note that Vt and β standard deviations are extracted using the new Y function mismatch extraction method proposed in section II.2.
Table of contents :
CHAPTER I TRANSISTOR MOSFET: THEORY, CHARACTERIZATION AND MISMATCH CONCEPT
I.1 MOSFET transistor
I.1.1 Operation principle
I.1.2 Electrical figures of merits for static performance
I.1.3 Operating Regimes
I.1.4 Parasitic effects due to the Miniaturization of MOS transistors
I.2 Methodology of extraction of MOS transistors parameters
I.2.1 Maximum slope method
I.2.2 Constant current method
I.2.3 Y function method
I.3 Types of electrical variability
I.4 Local variability
I.4.1 Measurement phase
I.4.2 Gaussian distribution verification
I.4.2.a Data plot
I.4.2.b Gaussian law verification
I.4.3 Data filtering and separation between systematic and stochastic mismatch
I.4.4 Concept and computation of systematic mismatch
I.4.4.a Concept of systematic mismatch
I.4.4.b Systematic mismatch computation
I.4.4.c Confidence interval
I.4.5 Stochastic mismatch
I.4.5.a Concept and computation of stochastic mismatch
I.4.5.b Confidence interval
I.4.5.c Deviations from Pelgrom‟s Law
I.5 Mismatch measurement system and test structures
I.5.1 Mismatch measurement system
I.5.2 Mismatch test structures
I.6 Stochastic mismatch contributions and effects in Bulk technology: state of the art.
I.7 Improvements due to FD SOI technology
I.7.1 Main advantages of SOI over BULK technology
I.7.2 Stochastic mismatch contributions and effects in FD SOI technology: State of the art
CHAPTER II NEW METHOD FOR THE EXTRACTION OF THE THRESHOLD VOLTAGE AND CURRENT GAIN FACTOR MISMATCH AND NEW DRAIN CURRENT MISMATCH MODEL
II.1 Introduction and motivation of this work
II.2 New Y-function based mismatch extraction method (strong inversion regime)
II.3 New drain current mismatch model
II.3.1 Validation of the new drain current mismatch model
II.4 Experimental Results
II.4.1 Experimental setup
II.4.2 FD SOI NMOS transistors of moderate gate length (W=1μm/L=0.1μm)
II.4.3 FD SOI NMOS transistors with short gate length (W=0.08μm/L=0.05μm)
II.4.4 Bulk NMOS transistors with short gate length (W=10μm/L=0.03μm)
CHAPTER III CASCODE CONFIGURATION AS A SUBSTITUTE TO LDE MOSFET FOR IMPROVED ELECTRICAL MISMATCH PERFORMANCE
III.1 Introduction and motivation of this work
III.2 Experimental details
III.3 Vt, β and ID mismatches comparison for LDEMOS, Individual and cascode configuration device
III.3.1 Linear Regime
III.3.1.a Vt and β mismatch
III.3.1.b ID mismatch
III.3.2 Saturation Regime
III.3.2.a Vt mismatch
III.3.2.b ID mismatch
III.4 Conclusions and perspectives
CHAPTER IV IMPACT OF GE PROPORTIONS IN P-MOSFET CHANNEL ON MATCHING PERFORMANCES IN 28NM GATE FIRST BULK TECHNOLOGY
IV.1 Introduction (State of the art)
IV.2 Experimental setup
IV.3 Electrical parameters mismatch characterization on transistors without pocket implants
IV.3.1 Threshold Voltage mismatch
IV.3.2 Current gain factor mismatch
IV.3.3 Drain current mismatch
IV.4 Electrical parameters mismatch characterization on transistors with heavily pocket implants
IV.4.1 Threshold Voltage mismatch
IV.4.2 Current gain factor mismatch
IV.4.3 Drain current mismatch
CHAPTER V MISMATCH CHARACTERIZATION OF 20NM GATE-LAST BULK CMOS TECHNOLOGY
V.1 Introduction (State of the art)
V.2 Experimental details
V.3 Comparison of devices with channel pocket implants and different oxide thicknesses EOT (Tox) in 20nm Gate-Last technology
V.3.1 Threshold Voltage mismatch
V.3.2 Current gain factor mismatch
V.3.3 Drain Current mismatch
V.4 Comparison between 28nm Gate-first and 20 nm Gate-last Bulk technologies
V.4.1 Threshold Voltage mismatch
V.4.2 Current gain factor mismatch
V.5 Vt and β mismatch trends as a function of Tox
CHAPTER VI MISMATCH BEHAVIOR IN ADVANCED FD SOI CMOS TECHNOLOGIES
VI.2 Mismatch behavior in 14nm and 28 nm FD SOI CMOS technology
VI.2.1 Experimental details
VI.2.2 Effect of EOT: Comparison between GO1 and GO2 for 14nm FD SOI technology
VI.2.2.a Threshold Voltage mismatch
VI.2.2.b Current gain factor mismatch
VI.2.3.c Drain current mismatch
VI.2.3 Comparison between 28nm and 14 nm FD SOI technologies
VI.2.3.a Threshold Voltage mismatch
VI.2.3.b Current gain factor mismatch
VI.2.4.c Drain current mismatch
VI.2.4 FD SOI technology mismatch summary and discussions
VI.3 Mismatch behavior with transistor aging in response to NBTI stress
VI.3.1 Brief description of NBTI Stress
VI.3.2 Experimental details
VI.3.3 Mismatch behavior in response to NBTI stress for GO1 and GO2 28nm FD SOI devices
VI.3.3.a Experimental results
VI.3.3.b Theoretical models and discussions
GENERAL CONCLUSIONS AND PERSPECTIVES