Modeling of gs dg mosfet in linear and saturation region

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MINIATURIZATION EFFECTS

Producing MOSFETs with channel lengths much smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometers, has created operational problems.
• Higher subthreshold conduction
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the « on » case and low current in the « off » case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.

Increased gate-oxide leakage
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.
Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards.
Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant.
• Increased junction leakage
To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, « halo » doping and so forth, all to decrease drain-induced barrier lowering. To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

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List of figures
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INTRODUCTION
CHAPTER I: DEEP SUBMICRON MOSFETs
I.1 – Introduction
I.2 – Evolution of CMOS technology
I.3 – MOSFET structure and operation
I.3.1. Presentation of the Structure
I.3.2. Operation Modes
I.4 – Small signal parameters
I.5 – Miniaturization effects
I.6 – Emergent solutions
I.6.1. High-k and metal gate integration
I.6.2. Strain-enhanced mobility
I.6.3. Multi-gate devices
I.7 – Nanotechnologies
I.8 – Conclusion
CHAPTER II :DEFECTS IN MOSFET DEVICES
II.1 – Introduction
II.2 – Defects classification
II.2.1 Bulk defects
II.2.2 Hot carrier
II.3 – Device degradation models
II.4 – Conclusion
CHAPTER III: MODELING OF GCGS DG MOSFET IN SUBTHRESHOLD REGION
III.1 – Introduction
III.2 – Model formulation
III.2.1. Surface potential
III.2.2.Threshold voltage
III.2.3. Subthreshold current
III.2.4. Subthreshold swing
III.3 – Results and discussion
III.4 – Conclusion
CHAPTER IV: MODELING OF GS DG MOSFET IN LINEAR AND SATURATION REGION
IV.1 – Introduction
IV.2 – Description of the studied structure
IV.3 – Proposed models formulation
IV.3.1. Piece-Wise Drain Current Models
IV.3.2. Surface potential based drain current model
IV.4 – Results and discussion
IV.4.1. Piece-Wise Drain Current Models
IV.4.2. Surface potential based drain current model
IV.5 – Impact of hot-carrier degradation on IC design
IV.6 – Conclusions
CONCLUSION AND FUTURE WORK
REFERENCES

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