Modeling of infinite ADPLL network by a continuous wave propagation medium

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Environment of the PhD project: the starting point and motivations

This PhD work is deployed in the framework of a research project at LIP6 laboratory focused on techniques of alternative clocking, started at 2007 and funded by two consecutive ANR grants (HODISS, 2008-20012 and HERODOTOS, 2011-2014). The project was focused on a study of a particular architecture of clock generation, based on a network of oscillators coupled by a network of All-Digital Phase Locked Loops. The goal of the project is a development of a novel clocking technique and its validation by design of two IC prototypes.
My PhD thesis is directly related to this objective. Before my arrival, the project were carried out by a PhD student Eldar Zianbetov who finished his PhD when I arrived, and a postdoctoral researcher Mohammad Javidan. Since the starting point of my PhD project was the result obtained by the previous work, in this section I will summarize the state of the project at that time. In Subsection 1.2.10 I will explain the shortcoming and challenges which motivated the opening of my PhD position, and in Section 1.3 I will present the objectives of my PhD.

Network of coupled PLLs for clocking: history of the concept

In 1995 Gill Pratt and John Nguyen proposed a distributed clock generator based on network of coupled analog PLLs [39]. Our work is based on this kind of architecture. For this reason, this subsection provides essential information about that.
The proposed clock generator belongs to the family of multioscillator architectures based on a network of coupled oscillators. In such a clocking scheme, Fig. 1.3, a chip is partitioned into local clock areas, each of them having its own clock generator (oscillator) which must be synchronized with its neighbors in the phase domain. The goal of the distributed PLL(phaselocked loop) network is to synchronize each oscillator in phase and in frequency. In a steady state, such a network is a source of fully synchronous distributed local clocks.

Presentation of an ADPLL network prototype designed at LIP6 prior to my PhD thesis

Fig. 1.7 presents the architecture of the network and the location on different blocks on a chip. A chip is divided into zones we call « SCA » (Synchronous Clock Areas, similarly as in GALS literature). In the center of each zone there is a digital loop control filter and a DCO (Filter/oscillator block (FO) in Fig. 1.7). Each phase frequency detector (PFD) is shared by two neighboring SCAs.
The structure of one network node (NODEi; j) in this specific ADPLL network is displayed in detail in Fig. 1.8. Compared with an analog PLL network in Fig. 1.4(b), it uses digital phase/frequency detector, a proportional-integral (PI) digital loop control filter, and a digitally controlled oscillator. Four clock signals generated by neighboring nodes around NODEi; j are used as references. PFDs quantize the phase differences between these reference signals and the locally generated divided clock. These quantized binary codes are summed by Error combiner and then processed by the PI filter, which updates the control signal for DCO at each cycle. The PI filter is sampled by the local divided clock, by consequence, this is a self-sampled system.
The following subsections Subsection 1.2.4 to Subsection 1.2.6 present the principles and implementations of these blocks designed in LIP6, and emphasize the features specifically related to the digital nature of this system.

Digital loop control of ADPLL network node

This subsection describes the digital loop corrector of node used in the 1st prototype designed at LIP6. The simplified architecture of this block is given in Fig. 1.8. This block processes the phase errors between the local clock and 2, 3 or 4 neighbors issued by the corresponding PFDs. The purpose of this block is to generate a control word for the input of the DCO. It includes two cascaded elements: an error combining block and a proportional-integral digital filter.
A detailed schematic of the implemented digital processing block is provided in Fig. 1.15. The block receives four 5-bit signed binary words as inputs, and generates a 10-bit unsigned word for the DCO control (the output of the adder ADD5). This signal is applied to the input of the DCO. The schematic in Fig. 1.15 includes the encoder converting this input binary code to the A, B and C signals necessary to control the DCO core. This encoder is described in Subsection 3.3.2.

Impact of quantization in ADPLL on its operation in steady state

Previous study presented in Subsection 1.2.8 focuses on the global stability of system, and not on the optimization of its operation in steady state when the whole system converges. Moreover, these studies were based on an analog model of the system, which did not account for quantization. Indeed, in an analog PLL network with 2 integrators in each node, in absence of noise, the residual error is zero[39]. However, it is not the case with all digital PLLs, because the PFD and DCO, which implement signal conversion between the analog and digital domains, introduce unavoidable quantization errors. Moreover, the digital filter operates at fixed point arithmetic, and rounding code applied to the DCO may also be a source of errors.
The study presented in this section provides a method aiming to minimize the absolute phase error between reference clock and divided DCO clock in steady state at a lowest DCO and PFD circuit implementation cost. Although this study is based on the model of one single PLL, it has an instructive meaning for the estimation of the quality of quantization in an ADPLL network. This method presented in the following three subsections is summarized as follows. First, the analysis presented in Subsection 2.3.1 estimates the relation between the residual error in steady-state and the parameters of the DCO and PFD individually. This analysis allows a rough selection of DCO and PFD.
Afterwards, in Subsection 2.3.2, the effect of quantization in the digital filter is highlighted and a solution is proposed. Thanks to this solution, for a target loop gain and a given DCO, we can estimate the required PFD resolution.
Then in the third step (cf. Subsection 2.3.3), behavior VHDL model considering quantization in the ADPLL is created. Time simulations using this model can show the residual error in steady state with different block parameters. Simulations validate our study in Subsection 2.3.1 and Subsection 2.3.2 and help estimating the optimal combination of parameters, which can minimize the residual phase error.

Step 1: Impact of PFD and DCO quantization steps on the residual error

In this step, we study the PFD and DCO blocks separately. First, we study the limit imposed by the finite resolution of PFD. In an ADPLL system, the residual phase error in steady state does not exceed two steps of TDC resolution (cf. Subsection 1.2.10). Hence, in the best case (optimal operation of the DCO and filter), the phase error expressed in time units between neighbors Dt will be in the following interval: 􀀀2DTTDC Dt 2DTTDC (2.1) where DTTDC is the TDC quantization step value in second. We define a parameter DtPFD which characterizes the maximal absolute phase error expressed in time unit due to quantization of PFD in the best case: DtPFD = 2DTTDC (2.2)
In this analysis we express the phase error in the time units, since such a phase error is invariant with regard to the frequency division.
Now we study the limit imposed by the quantization of the DCO characteristic. The objective of a PLL is to equalize the phase of the feedback signal coming from the DCO and divider, on the signal of the input reference (Fig. 1.6). It means that the PLL feedback signal have the same frequency as the input reference signal. However, whereas the input signal can have any frequency belonging to some continuous interval, the DCO generates a signal whose frequency belongs to a discrete grid of values. When the DCO signal passes through a divider, the frequency values are downscaled, but remain discrete. Hence, if the PLL input (reference) frequency is between two neighboring values of the divided grid, the PLL closed loop generates a variable input DCO code, so that the output frequency of the DCO switches permanently between the two corresponding values of the grid. This is done with the help of feedback loop which minimizes the phase error.

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Step 2: impact of rounding in digital filter on the correction of residual phase error

This section presents the problems related to the rounding in the digital filter of the ADPLL, and proposes some solutions. As in previous subsection, the analysis will be demonstrated 2.3. Impact of quantization in ADPLL on its operation in steady state 41 on a single ADPLL using the analytical model presented in Subsection 1.2.7, but the results are also valid for a network of ADPLLs.
The filter receives integer words, and the input of the DCO is integer as well (arbitrarily, it is possible to define fractional and integer part of the DCO word, but the simplest choice is to consider DCO input as an integer). However, in the filter, the proportional coefficient a and integral coefficient b (as shown in Eq. (1.2)) are generally not integers, but as said in Subsection 1.2.5, the output of the proportional and integral branches are rounded.
The rounding of the integral branch is fundamentally harmful, since it limits the precision of the output frequency definition. But the origin of this rounding is not in the integral branch itself, but in the limited width of the DCO input word, (equivalently, in the limited DCO resolution). The discretization the DCO frequency value is a fundamental property of an alldigital PLL, which is supposed to be corrected thanks to the modulation of the input DCO word between two neighboring values.
However, the most important danger for the ADPLL operation is the rounding in the proportional part. Imagine that a is smaller than 1. In this case, small phase error xi such that xi a < 1, yields a zero output of the proportional path, as if a was zero. Hence, small error cannot be corrected by proportional path, and it is well known that a PLL with a zero proportional path oscillates [14]. In the context of digital PLL, a small a leads actually to a variable a: for large errors it has its nominal value, but for small errors it is zero. Such an ADPLL exhibits an output phase error oscillating with amplitude corresponding to the limit between the modes « rounding of small error » and « correct detection of big error ». In contrast, an a larger than 1 is equivalent to a normalized a with an enlarged DCO tuning step (a reduced resolution). For instance, if a equals 2, in steady state, instead of switching between two adjacent frequency values, the DCO changes at least two steps each time. In this case, the high resolution of the designed DCO is wasted.

Table of contents :

1 Introduction 
1.1 Area of focus
1.1.1 Problem of clocking in large digital circuits
1.2 Environment of the PhD project: the starting point and motivations
1.2.1 Network of coupled PLLs for clocking: history of the concept .
1.2.2 Digital phase synthesis
1.2.3 Presentation of an ADPLL network prototype designed at LIP6 prior to my PhD thesis
1.2.4 Phase frequency detector (PFD)
1.2.5 Digital loop control of ADPLL network node
1.2.6 Digitally controlled oscillator (DCO)
1.2.7 Modeling of ADPLL and of ADPLL network
1.2.8 Stability of the PLL networks
1.2.9 Multiplicity of synchronization modes
1.2.10 Discussion of test results of the implemented prototype
1.3 Original contribution of my PhD project
1.4 Thesis outline
2 Network of distributed ADPLLs 
2.1 Introduction
2.2 The architecture of clocking network proposed in this PhD project
2.3 Impact of quantization in ADPLL on its operation in steady state
2.3.1 Step 1: Impact of PFD and DCO quantization steps on the residual error
2.3.2 Step 2: impact of rounding in digital filter on the correction of residual phase error
2.3.3 Step 3: validation of block parameters by transient simulations
2.4 Specification of the network
2.5 Conclusion
3 ADPLL blocks design 
3.1 Phase frequency detector (PFD)
3.1.1 The digital PFD architecture
3.1.2 Improvement of time-to-digital converter
3.1.3 Implementation of PFD
3.2 Digital filter in the ADPLL network
3.2.1 Architecture of digital filter
3.2.2 Implementation of the filter
3.3 Digitally controlled oscillator (DCO)
3.3.1 DCO Architecture
3.3.2 Control algorithm
3.3.3 Implementation
3.3.4 Serial programming interface (SPI)
3.3.5 Simulation results
3.4 Conclusion
4 Built-In Clock Error Characterization Circuit 
4.1 Introduction
4.2 State of art
4.3 Test methodology
4.3.1 Measurement theory
4.3.2 Architecture of measurement circuit
4.4 Low frequency discrete circuit prototype
4.5 High frequency on-chip prototype
4.5.1 Voltage-controlled delay (VCD)
4.5.2 Physical design of test circuit on silicon
4.5.3 Modeling of clock generator for system verification
4.5.4 Simulation results
4.6 Procedure of measurement
4.7 Conclusion
5 Clock network FPGA prototyping 
5.1 Introduction
5.2 Implementation of FPGA based blocks
5.2.1 Synthesizable DCO
5.2.2 Synthesizable TDC
5.3 Experimental results
5.3.1 Stability and prevention of mode-lock
5.3.2 Phase error between two remote local clocks
5.4 Conclusion
6 Clock network silicon implementation 
6.1 Introduction
6.2 Methodology of chip design
6.3 Implementation of local clock generator (NODE)
6.4 Floorplan of the chip
6.5 Design for test(DFT)
6.5.1 Chip programming
6.5.2 Built-in test circuits placement
6.5.3 Definition of the input/outputs of the chip
6.6 Chip layout
6.7 Simulation results
6.8 Conclusion
7 « Swimming pool »-like distributed architecture 
7.1 Introduction
7.2 Modeling of infinite ADPLL network by a continuous wave propagation medium
7.2.1 From a discrete network to a continuous medium
7.2.2 An analogy with damped wave equation
7.3 ADPLL network with limited surface
7.4 Simulation results
7.5 Conclusion
8 ADPLL with sliding-window for wide range frequency tracking 
8.1 Introduction
8.2 State of art
8.3 « Sliding window » architecture
8.3.1 Reference frequency indicator (RFI)
8.3.2 Coarse frequency adjustment
8.3.3 Phase error correction
8.4 Comparison with conventional PLL
8.4.1 Functional Simulation results
8.4.2 Power consumption comparison
8.5 Clock distribution network using « sliding window » ADPLL
8.5.1 Network structure
8.5.2 Evaluation of functional performance of system
8.6 Conclusion
9 Conclusion and Perspectives 
9.1 Thesis summary and conclusions
9.2 Future work
9.2.1 Modelling of ADPLL for the study of residual phase error in steady state
9.2.2 Exploration of fault-tolerance property
9.2.3 Clock distribution for 3-D chip
A VHDL models of the ADPLL blocks 
B VHDL models for built-in test circuit 
C Matlab scripts 
D FPGA prototyping of the clocking network 
E Tcl script for automatic floorplan of network 


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