MOSFET in the 28 nm UTBB FD-SOI technology
The MOSFET in thin-film FD-SOI is a four-terminal device: the gate, the back-plane – or substrate (which can also be considered as a back gate) -, the source and the drain. It is mainly used as an electrical switch. Indeed, by controlling the gates’ voltages, the transistor can let the current pass between the source and the drain (in logic it is called a “1” and the transistor is considered ON) or block it (then it is a “0” and the transistor is OFF). The transistors can be of type N (then the carriers flowing from one side of the channel to the other are electrons) or P-type (the carriers are holes). Here are the different features of the MOS transistors in the 28 nm FD-SOI Ultra-Thin-Body and BOX (UTBB) technology node: two types of back-plane (NWELL and PWELL doping) make it possible to get two different threshold voltages for each type of MOSFET. If the doping is the same type in the back-plane and in the channel, it is a LVT (Low Threshold Voltage) transistor, else it is a RVT (Regular Threshold Voltage) transistor (Figure 3). The structure of the RVT N-MOS FD-SOI transistor is described in Figure 4. In the NRVT MOS, the channel of the transistor is left undoped (Pint doping). The source and the drain are epitaxially raised for reducing the access resistance, and their doping is N+. The lightly doped extensions of the source and the drain (N-LDD doping) are here to limit the lateral electric field (indeed, the reduction of the lateral field is less abrupt with extensions, because it is staggered all along the extension) in order to attenuate hot carrier degradation. The goal of the spacer is to limit the prolongation of the lightly doped extensions under the gate. The metallic gate is made with polysilicon and titanium nitride. This material has been chosen for its work function, because it is a mid-gap material allowing to have equilibrate threshold voltages between the NMOS and the PMOS . In the 28 nm FD-SOI technology that is used in STMicroelectronics    , the channel is very thin (TSi = 7 nm) for a better electrostatic control of the gates on the channel. The BOX is 25 nm thick. Under the BOX, the back-plane is P-doped (PWELL doping). The NISO doping (or deep NWELL) is used to isolate this PWELL doping from the rest of the substrate. On top of source, drain and gate, salicidation is realized to reduce the access resistance, and then metallic connections are made. The transistor is insulated from others thanks to oxide trenches named STI (Shallow Trench Isolation).
When a positive bias is applied on the gate (VG), a conductive N-channel (made of electrons) takes place in the silicon channel under the gate oxide between the source and the drain, and a vertical electric field is created in the oxide. If a positive bias is also applied on the drain (VD), a lateral electric field is generated, and the carriers in the conductive channel can move from source to drain; this leads to a current ID. Polarizing the substrate can have some interests for example in case of threshold voltage tuning. The different modes of the transistor operation are seen on the ID vs VG curve for a fixed VD (Figure 5), for example VD = VD_USE > VDSAT:
– The transistor is blocked when VG = 0 V (ID = IOFF)
– It is in weak inversion when VG < VTH
– It is in strong inversion when VG > VTH (usually ION is selected at VG = VD_USE).
VTH is the threshold voltage delimiting the two states (weak and strong inversion). The Subthreshold Slope (SS) is extracted from the curve slope below VTH while plotting ID vs VG in logarithmic scale: Its theoretical limit is 60 mV/decade at 300 K. IOFF is undesirable because it corresponds to a leakage current increasing power consumption when transistors and circuits are in standby mode.
If the thickness of the gate oxide (Tox) is reduced, then the gate control on the channel is enhanced, but the possibility that carriers cross the potential barrier of the gate oxide by tunnel effect is increased. The resulting leakage current between the channel and the gate – but also between the gate and the source or drain junctions (because of the underlap) – is then stronger. Silicon oxide is replaced by high-k dielectrics in order to minimize this effect; indeed, the thickness of the oxide can be larger for a same value of capacitance of the gate oxide. That is why the term of EOT (equivalent oxide thickness) is employed. An interfacial layer of SiO2 is necessary to be able to deposit HfO2 above the silicon thin-film. GO1 (thin oxide) RVT transistors have a VD_USE = VDD of 1 V and GO2 (thick oxide) transistors have a VDD of 1.8 V. The typical threshold voltage of a GO1 RVT transistor is about 0.4 V.
The electrostatic discharge
Definition of ESD and importance of ESD protections
An electrostatic discharge (ESD) is the sudden flow of current between two electrically charged objects (“The rapid, spontaneous transfer of electrostatic charge induced by a high electrostatic field.” ). In the everyday life, one can experience it – for example – by feeling a spark when touching the door of a car or walking on a carpet. Another very common example of discharge is a lightning bolt. ESDs can be caused by triboelectricity, induction or direct conduction, and happen all the time, involving different orders of magnitude of current and voltage. A human has to be charged to 3 kV minimum in order to be able to feel the ESD, he has to be charged to 5 kV to hear it and to 10 kV to see a spark . In the industry, electronic circuits are supposed to undergo ESDs up to 4 kV at component level, and multiple amperes in a few nanoseconds, which may already be destructive if the circuit has not been protected. As a matter of fact, more than 50% of all failures are attributed to ESD and EOS (Electrical OverStress), ESD being a subset of EOS (Figure 6) . “Electrical overstress (EOS) is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product and causes it to fail (reversibly or irreversibly, immediately or delayed).” 
An ESD event can damage the oxides , junctions, metals , and the plastic of the package of the circuit, as well as produce hot carrier degradation and melting (Figure 7). For example, the discharge can provoke an increase in drain voltage on a transistor, therefore increasing the electrical field between the drain and the gate. When this field is too high the gate oxide is damaged  , which induces leakage current in the MOSFET, or even a short circuit between the drain and the gate. In the channel, discharges increase the temperature . The semiconductor can reach fusion and conductive filaments  can be created between the source and the drain. Due to the high voltages, impact ionization occurs, therefore hot carriers  are generated and injected into the oxides, damaging them and increasing the leakage in the MOSFET. A critical value of electron trap density injected into the oxide leads to gate oxide breakdown  . In the metallic vias and interconnections, a discharge can cause electro-migration or simply increase the temperature by Joule effect, and some melting can occur, thus cutting the line. Metal filaments can also intersect junctions in the devices . As a consequence, soft damage (aging) or even hard damage (immediate breakdown) happens . As a matter of fact, there is a need in protecting integrated circuits from ESDs in the industry.
ESD stress standards
An infinite type of discharges is possible with large energy deposition, and it can be very expensive to develop methodologies to protect ICs from ESDs. That is why the ESDA (ESD Association) has been created to establish standards and share the improvements and developments between industrials and researchers. In this framework, three main models of ESD are used in microelectronics:
– The Human Body Model (HBM) describes a discharge from a charged human to the device.
– The Machine Model (MM) is used to mimic a discharge from a charged machine touching the device.
– The Charged Device Model (CDM) is used when the component is charged itself and the discharge is transferred to another object.
Those different configurations are represented each by an RLC equivalent circuit; thus, a second order differential equation can describe the ESDs.
Those models correspond to component-level test methods, useful for estimating the robustness of circuits in a manufacturing environment, while system-level ESD testing (or Gun testing) is relevant for final product testing. To predict the ESD performance under system-level stress condition, the Human Metal Model (HMM)   has been proposed by the ESDA. Cable Discharge Event (CDE)    should also be taken into account for the qualification of products. This manuscript only deals with component-level tests so system-level tests are only mentioned for information purpose.
Human Body Model
For the HBM , the charge transfer happens when a charged person is touching the integrated circuit. The current is flowing from the touched pin of the chip to another one that is grounded. All the other pins are supposed to be left floating. The equivalent electrical circuit of this HBM discharge is depicted in Figure 8. The contact of the person touching the chip is considered of being a resistor of 1.5 kΩ (this is why RESD = 1.5 kΩ). CESD = 100 pF is representing the body capacitance of the person with respect to the ground. The impedance of the Device Under Test (DUT) is neglected (hypothesis of a short circuit: the model is valid when considering that the ESD protection device – which is the DUT – is ON because the ESD event was detected), as well as the parasitic capacitances of the tester (that is subject to a maximum number of tested pins). The inductance of the tester (used to test the device as if it was undergoing an HBM discharge) is considered (LESD = 7.5 µH). CESD is charged to a specific ESD voltage, then the contact is established and the discharge happens. The intensity of the discharge depends on this pre-charge voltage, considered as VHBM = 1 kV for RF (radio frequency) applications and 4 kV for more challenging environment such as military applications. The ESDA is constantly making those voltage requirements evolve because it is more and more difficult to provide on-chip ESD protection devices that are able to stand such high voltages. More and more protection devices are characterized and approved for being able to stand VHBM = 500 V and less . In real manufacturing environment, the pre-charge voltage is limited by preventive actions such as operators wearing wristbands and foot straps to dissipate the discharge, equipments being grounded, humidity control, etc.
For the MM , the same conditions are applied (same equivalent circuit as for HBM). This time, since it is a machine touching the IC and not a human, RESD is way smaller: RESD = 10 Ω for simulating a metallic contact. The typical VMM is situated between 100 V and 500 V. CESD = 200 pF and LESD is considered between 0.5 µH and 2.5 µH.
As a result, the waveforms present oscillations. Those oscillations are smoothed after a hundred of nanoseconds (Figure 10). Because of the small RESD, they are strongly dependent on the tester, therefore the tests are not really reproducible. The MM is no longer considered as a qualification standard: it has been assessed that meeting the HBM and CDM industry standard was sufficient for the component manufacturer .
Charged Device Model
The CDM  is for the case when the charged device is discharging itself to another object. The current flows from everywhere in the circuit toward a single stressed pin which is grounded. It is the most difficult surge to protect the circuit for, because protections have to be placed within the core of the integrated circuit in addition to all the pins. To be CDM qualified, a particular test bench is required, and the DUT is charged thanks to either Direct Charging Method or Field-Induced Charging Method. In this manuscript however, the same method of measurement is used to simulate a CDM discharge and an HBM one (see the section about TLP and VF-TLP measurement).
The equivalent electrical circuit of a CDM is shown in Figure 11. The pre-charge voltage VCDM is taken between 125 V and 1 kV. CESD corresponds to the capacitance of the circuit to be protected and can vary between 4 pF and 50 pF  . LESD is considered between 2.5 nH and 6.5 nH. RESD = 10 Ω like for MM. This small RESD leads to Δ < 0.
ESD design window
In order to protect circuits from electrostatic discharges, there are two types of complementary strategies. The first one consists in preventing discharges to happen, thanks to the management of the fabrication environment of the circuit: grounding all the surfaces that can touch the components to be fabricated, using antistatic surfaces and coatings, controlling the humidity in the air and so on. However, this is not sufficient and some discharges still arise. The second strategy aims at deviating the discharges on the circuit so that they do not affect the components of the core, thanks to dedicated protection devices.
The role of the ESD protection is to evacuate a sufficient amount of current while limiting the voltage at the terminals of the protected region, in case of ESD event, so that this destructive current does not pass by the operating part of the IC. The ESD protection should be transparent in the normal IC operating mode; this means that at the operating voltage VDD its leakage current Ileak is as low as possible, and the ESD structure is not active. Its parasitic capacitance is low in order to maintain the integrity of rapid signals . The ideal anode current versus anode voltage curve (Figure 14) corresponds to a device that is normally OFF but able to switch abruptly, at a given trigger voltage, in ON mode. This trigger voltage is called VT1. If the curve features a snap-back, the holding voltage, VH, is the smallest voltage applied on the device while it is in ON state; and when the device is conductive, it has a resistivity of RON. Without snap-back, the I-V curve is close to a straight line with a slope 1/RON starting at VT1. IT2 and VT2 correspond to the failure current and voltage, respectively. The ESD protection should activate before the components of the integrated circuit suffer from breakdown, at the voltage VBD. Therefore, there is a design window, establishing that the ESD protection is ON (i.e. low impedance) for a certain voltage range [(VDD+10%) – (VBD-10%)] only. If VH is too close from VDD, there is a risk of Latch Up (LU); it means that once the protection device is activated, it stays ON even if the discharge energy is evacuated and the circuit is back to its normal operational mode. This is why a margin of 10% has to be taken. The design window depends on the IC to be protected. The ESD protection should be efficient and robust: it does not break before having sufficiently protected the IC. This means that its failure current IT2 is the highest possible. In fact, IT2 should exceed the value of the peak current of the HBM discharge corresponding to the required norm (for example 1.2 A for a 2 kV HBM). The triggering should be very fast, because ESDs happen over a short time (1 – 100 ns).
Table of contents :
Chapter 1: Introduction
I. Presentation of the technology
1. Introduction to the FD-SOI technology
2. MOSFET in the 28 nm UTBB FD-SOI technology
II. The electrostatic discharge
1. Definition of ESD and importance of ESD protections
2. ESD stress standards
a. Human Body Model
b. Machine Model
c. Charged Device Model
3. ESD design window
4. Protection strategies
a. Local protection strategy
b. Remote protection strategy
c. Distributed protection strategy
III. Context of study and tooling
a. TLP measurements
b. VF-TLP measurements
c. DC measurements
2. TCAD as a predictive tool of investigation
a. Setup of the TCAD simulations
b. Average Current Slope and Average Voltage Slope
IV. ESD Protection devices
2. Protection devices built from NMOS devices
a. MOS switch
b. Grounded Gate NMOS
c. Bipolar MOS
3. Protection devices built from the SCR
a. Silicon Controlled Rectifier
b. Zero subthreshold swing and Zero impact ionization FET
c. Gated Diode NMOS
d. Beta-Matrix architecture
Chapter 2: ESD thin film devices
I. ESD boost solution for MOSFET and BIMOS
II. GDxMOS device for high and low-voltage ESD protection
1. GDxMOS as a high voltage protection
a. ESD robustness measurements
b. Influence of the front gates on the GDNMOS
c. Comparison between GDNMOS and GDBIMOS
d. Influence of the back gate on the GDBIMOS
e. Drain connectivities
2. GDxMOS as a low-voltage protection
a. Low-doped drain GDNMOS
b. Low-doped drain GDBIMOS
3. Silicide management in the GDxMOS
a. Silicide removal
b. Partial silicide
c. Partial silicide and drain connected to the diode gate
d. Partial silicide and drain connected to the anode
e. Fragmented partial silicide
Chapter 3: BIMOS matrices
I. BIMOS dot topology
1. 1D BIMOS dot
2. Matrix of BIMOS dot
II. Comparison of different BIMOS devices
1. Devices description
2. Results and discussion
Chapter 4: 3D ESD protections in FD-SOI
I. FD-SOI silicon continuity with bulk
II. 3D BIMOS merged SCR with silicon continuity
1. BIMOS merged SCR using P-doped trigger
2. BIMOS merged SCR using N-doped trigger
III. In-situ coupled bias resistance
1. In-situ coupled bias resistance in thin silicon film
2. In-situ coupled bias resistance in hybrid bulk
Appendix 1: TCAD setup
Appendix 2: AVS behavior of the BIMOS
Appendix 3: Résumé étendu en français
Chapitre 1 : Introduction
I. Contexte et objectifs
II. Présentation du MOSFET en technologie FD-SOI
III. Les décharges électrostatiques
1. Définition des ESD et importance des protections
2. Stress ESD standards
3. La fenêtre de conception ESD
4. Les stratégies de protection
IV. Outils de caractérisation
1. Mesures DC, TLP et VF-TLP
2. Outil TCAD : les simulations ACS et AVS
V. Les composants de protection contre les ESD
1. Diode de protection
2. Protections à base de NMOS
3. Protections à base de SCR
Chapitre 2 : Protections ESD dans le film mince
I. Boost capacitif pour NMOS et BIMOS
II. Le GDxMOS, protection ESD pour haute et basse tension
1. Le GDxMOS en tant que protection haute tension
2. Le GDxMOS en tant que protection très basse tension
3. Gestion du siliciure dans le GDxMOS
Chapitre 3 : Matrices de BIMOS
I. La topologie BIMOS dot
1. BIMOS dot en 1D
2. Matrice de BIMOS dot
II. Comparaison de différents BIMOS
Chapitre 4 : Protections ESD 3D en technologie FD-SOI avec continuité de silicium
I. BIMOS fusionné avec un SCR en 3D
II. Résistance fusionnée
1. Résistance fusionnée dans le film mince
2. Résistance fusionnée dans le substrat