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**BACKGROUND TO THE RESEARCH **

Data traffic of future telecommunication systems is projected to increase 10 000-fold in the next 20 years [1]. Various approaches have been proposed to meet the increase in throughput and can be grouped into three categories, namely: improving spectral efficiency, increasing spectrum availability and the massive densification of small cells. Spectral efficiency can be improved by techniques such as multiple input multiple output (MIMO), carrier aggregation, coordinated multipoint, heterogeneous networks, authorized shared access, as well as various interference cancellation techniques. This approach will, at best, only provide a 1000-fold speed improvement [1]. Increasing spectrum availability by moving to higher mm-wave frequencies (30 – 300 GHz) is, therefore, inevitable. In turn, the migration to mm-wave frequencies, practically, also implies the massive densification of the network through the deployment of small cells, due to the high atmospheric attenuation of mm-waves compared to microwaves. Next generation 5G fronthaul links will therefore be comprised of a mesh network of small-cells operating in the mm-wave spectrum with some preliminary International Telecommunication Union (ITU) specifications set for the V-band (57-66 GHz) and E-band (70-90 GHz) where contiguous bands of up to 5 GHz are available.

**Research gap **

Any delay function can be synthesized by cascaded first- and second-order all-pass networks [26], [27], with two cascaded first-order networks being a special case of the latter. Although various off-chip realizations of all-pass networks have been proposed in the peer-review literature [12], [13], [24], [28]–[32], their monolithic integration in commercial CMOS and BiCMOS technology nodes has presented a number of yet unsolved challenges. Implementing all-pass networks on-chip in a commercial technology node allows mass production at reduced costs and operating power requirements which is key to successfully replacing certain DSP tasks with ASP equivalents. However, several research gaps must be addressed before the synthesis and monolithic integration of all-pass networks is possible.

**RESEARCH OBJECTIVE AND QUESTIONS **

This thesis investigates, firstly, the synthesis of quasi-arbitrary group delay functions with a prescribed delay response (corresponding to certain ASP applications) using a minimum-order all-pass network, and secondly, the practical microelectronic implementation of the all-pass network on-chip, in the commercial CMOS and BiCMOS technology nodes. This will enable monolithic integration of ASPs on-chip, making the analogue approach a viable alternative to existing DSP techniques.The primary research question addressed in this thesis can therefore be stated as follows. How can a quasi-arbitrary group delay function be synthesized with a minimum-order network and implemented on-chip in commercial CMOS and BiCMOS technology nodes? The following derived (secondary) research questions arise.

1. What class of delay functions can be approximated by all-pass networks? What is the minimum order approximation? What is the error of approximation? How can this error be minimized?

2. How can existing all-pass networks be improved to obtain larger delay Q-value (QD)? Is an inductorless solution practically viable?

3. How do process tolerances and parasitic elements affect the design of the all-pass network? What can be done to reduce the network’s sensitivity to these non-ideal effects? If sufficient sensitivity reduction is impossible, can post-production tunability be used to compensate for these effects?

4. What can be done to increase the bandwidth of the all-pass network? Is a mm-wave bandwidth solution possible?

**METHODOLOGY **

First, a literature review is conducted and shortcomings in the state-of-the-art identified. The literature review is presented in three parts: delay function network synthesis, physical realization of all-pass networks and ASP applications.

**CHAPTER 1 INTRODUCTION**

1.1 BACKGROUND TO THE RESEARCH

1.1.1 Context of the problem

1.1.2 Research gap

1.2 RESEARCH OBJECTIVE AND QUESTIONS

1.3 METHODOLOGY

1.4 OVERVIEW OF STUDY

1.5 DELIMITATIONS TO THE SCOPE OF THE RESEARCH

1.6 CONTRIBUTION TO THE FIELD

1.7 RESEARCH OUTPUTS

1.8 CONCLUSION

**CHAPTER 2 LITERATURE REVIEW**

2.1 INTRODUCTION

2.2 DELAY FUNCTION NETWORK SYNTHESIS

2.2.1 Analytical synthesis techniques

2.2.2 Numerical synthesis techniques

2.3 PHYSICAL REALISATIONS OF ALL-PASS NETWORKS

2.3.1 Passive realizations

2.3.2 Active realizations

2.4 SECOND GENERATION CURRENT CONVEYORS

2.4.1 Introduction and operating principles

2.4.2 CMOS realizations

2.4.3 BiCMOS realizations

2.5 STABILITY ANALYSIS TECHNIQUES

2.5.1 Single-loop stability

2.5.2 Multi-loop stability

2.6 ANALOGUE SIGNAL PROCESSING WITH ALL-PASS NETWORKS

2.6.1 Real-time spectrum analysis

2.6.2 Frequency sniffing for cognitive radio

2.6.3 Arbitrary frequency beam scanning in antenna arrays.

2.6.4 Dispersion code multiple access (DCMA)

2.6.5 M-ary pulse position modulation (PPM)

2.7 CONCLUSION

**CHAPTER 3 RESEARCH METHODOLOGY**

3.1 INTRODUCTION

3.2 JUSTIFICATION FOR THE PARADIGM AND METHODOLOGY

3.3 OUTLINE OF THE METHODOLOGY

3.4 SIMULATION SOFTWARE.

3.5 MANUFACTURING PROCESS

3.6 MEASUREMENT SETUP

3.6.1 CMOS second-order all-pass network

3.6.2 CMOS CCII+

3.6.3 BiCMOS second-order all-pass network

3.7 CONCLUSION

**CHAPTER 4 MATHEMATICAL SYNTHESIS**

4.1 INTRODUCTION

4.2 THEORY OF GROUP DELAY SYNTHESIS

4.2.1 Approach

4.2.2 Theoretical derivation

4.3 APPLICATION EXAMPLES

4.3.1 Example 1: Synthesis of a linear group delay function

4.3.2 Example 2: Synthesis of Gaussian and quadratic delay functions

4.3.3 Example 3: Equalization of measured BPF group delay response

4.4 COMPARISON OF PROPOSED METHOD WITH EXISTING APPROACHES IN THE LITERATURE

4.5 CONCLUSION

4.6 MATHEMATICAL DERIVATIONS

4.6.1 Derivation of Theorem 1

4.6.2 Derivation of Theorem 2

4.6.3 Derivation of (4.8)

**CHAPTER 5 ON-CHIP IMPLEMENTATION OF ALL-PASS NETWORKS**

5.1 INTRODUCTION

5.2 CMOS ALL-PASS NETWORK

5.2.1 Introduction

5.2.2 Second-order all-pass network synthesis method

5.2.3 CMOS implementation of second-order all-pass network

5.2.4 Measurement Results and post-production automated tuning

5.2.5 Conclusion

5.3 SECOND GENERATION CURRENT CONVEYOR WITH CONTROLLABLE FEEDBACK

5.3.1 Introduction

5.3.2 Multi-loop feedback stability considerations in analogue circuits

5.3.3 Practical implementation of a high-precision, high bandwidth CCII+

5.3.4 Multi-loop feedback analysis application – astable example.

5.3.5 Conclusion

5.4 BICMOS ALL-PASS NETWORK DESIGN AND RESULTS

5.4.1 Introduction

5.4.2 Design

5.4.3 Results

5.4.4 Conclusion

5.5 CONCLUSION

**CHAPTER 6 CONCLUSION**

6.1 INTRODUCTION

6.2 CRITICAL EVALUATION OF RESEARCH QUESTIONS

6.3 CHALLENGES AND LIMITATIONS

6.4 SUGGESTED FUTURE WORK

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SYNTHESIS AND MONOLITHIC INTEGRATION OF ANALOGUE SIGNAL PROCESSING NETWORKS