Chapter 2. Topology Comparison and Evaluation
Project Requirements and Converter Specifications
The motivation for this work, as mentioned in the introduction, is primarily to develop an efficient, bidirectional, low noise DC/DC converter for use in UPS applications. There were a number of different DC/DC topologies considered   , but due to the nature of the project, there were some topologies which were not considered entirely. For example, due to the time constraints of the project, it was determined that isolated converters would not be considered as these topologies would be too time-consuming to design and construct. Additionally, due to the desire to maximize power density, it was desirable to make the DC/DC converter with as few components as possible in order to easily determine the best physical layout to minimize the volume of the UPS.
Additionally, as the inverter and rectifier stages of the UPS were three-level NPC modules, the DC link of the system consists of two capacitors in series, splitting a total 800 V DC bus into two split buses at 400 V each. For this reason, it was determined that there may be some additional advantage of having a DC/DC converter which would be able to transfer power to and from either of the DC link potentials and battery backup. Finally, the common-mode noise profile of the converters was to be considered. As previously explained, the noise profile of the DC/DC converter will affect the overall noise profile of the UPS. Therefore, it is beneficial to consider the natural noise profile of the DC/DC converter to see if any topologies have an advantage over others simply due to their operation.
The first topology considered was a simple buck converter. This converter is the simplest proposed topology as it consists of only two switches. Additionally, due to the limited number of active devices, it was anticipated that the buck converter would have very high efficiency as the conduction losses will be at a minimum compared to other topologies which include multiple devices.
However, the simplicity of the buck converter also comes with some disadvantages. For example, the buck converter is only able to utilize one input potential and one output potential. This means that the simple buck converter will only be able to transfer power from the entire DC link, the upper DC link, or the lower DC link. Also, due to the natural asymmetry of the buck converter, there is no way to reduce the common mode voltage profile of the converter without adding filters. As the buck converter is very well known and there is very little variation available with regards to the switching sequence of the converter, its operation will not be discussed in detail.
Three-Level Buck Converter
The next topology considered is a three-level buck converter. This is the topology which is the main subject of this paper. This topology consists of four SiC MOSFETs arranged in a three-level neutral-point-clamped configuration. This configuration is the same as that used by the inverter and rectifier stages of the UPS. In comparison to the simple buck converter, this topology has the added benefit of additional switching sequences which may be used for different desired functionality. Also, this converter does have a connection to the DC neutral point of the DC bus. This means there may be asymmetrical power flow between the DC link and battery.
Note that there are a number of diodes included in the schematic above which do not appear to be critical to the function of this converter. This is because the topology shown above is that of the actual NPC module used in the inverter and rectifier stages of the UPS. Although these diodes are necessary for AC/DC conversion, they are extraneous in the operation of the three-level buck converter. They are only included here for the sake of completeness.
One last major benefit of this topology is the ability to decouple each pair of switches from one another to achieve different results. The upper two switches and lower two switches must operate in a complementary fashion in order to prevent a short-circuit condition with the DC bus. However, the switching sequences of each pair with respect to one another can be anything. This means the duty cycles of the two pairs can operate synchronously, complementary, or with a phase-shift to achieve different results in each case. The traditional applications for this type of converter utilize this phase shifted operation to halve the output current ripple. However, when there is no phase shift and the two pairs operate synchronously, there is ideally no common-mode voltage generated, which is beneficial for noise. The synchronous operation is shown below.
In this mode of operation, the topmost and bottommost switches operate synchronously. As the middle devices must operate in a complementary fashion to their adjacent outermost devices, they also operate synchronously with one another. This mode of operation allows the converter to maintain a symmetric voltage profile with respect to the battery, meaning there should be no common-mode voltage output under ideal conditions. The phase-shifted mode of operation is shown below as well.
As demonstrated in the preceding figures, there are two slightly different switching sequences for the phase-shifted operation. This is because the battery voltage is not constant, and will increase or decrease as it is charged or discharged, respectively. When the battery voltage is less than half of the total DC link voltage, a freewheeling state is necessary to maintain volt-second balance. However, when the battery voltage is greater than half of the total DC link voltage, this freewheeling state is replaced by a state whereby the entire DC link transfers power to the battery.
One of the topologies investigated was a PEBB-based converter which can also be constructed using three-level NPC inverter modules. This converter uses two such modules and the battery is connected between the outputs of each of these converters. This topology was considered as it has a distinct advantage of offering more switching states than any other topology discussed. It was investigated whether this would provide any additional noise and/or output current ripple benefit in comparison to the other topologies discussed.
The two main drawbacks of this converter are efficiency and the number of modules needed to construct it. The efficiency is expected to be low due to high conduction losses. At any given time, this converter will always have more devices conducting current than the simple buck converter. Additionally, 8 devices are needed for this topology compared to the two needed by the buck converter and 4 needed by the three-level buck converter.
The operation of this converter is very similar to that of the three-level buck converter as it is also a three-level NPC variant. However, as the battery is connected between the outputs of two NPC phase legs, their switching states are slightly different. Once again, there is a synchronous operation mode and a phase-shifted operation mode. Both operating modes are shown in the following figures.
It is also important to note that the PEBB-based converter has two additional freewheeling states which can be utilized by turning on the upper two or lower two switches of both NPC phase legs. This allows the current stored in the battery filter inductor to freewheel at either the positive or negative DC bus potential. This also comes at the cost of potentially higher conduction losses as two devices must conduct for this freewheeling to occur. The current may also pass through the device antiparallel diodes on one side of the battery for this freewheeling operation.
Interleaved Three-Level Buck Converter
The last topology considered is an interleaved version of the three-level buck converter discussed in section 2.3. This topology operates under the same principles as the non-interleaved three-level buck converter, but due to interleaving, it is able to halve the output current ripple and provide twice the output power when compared to the single three-level buck converter case. This topology possesses all the same benefits of the three-level buck including asymmetric power transfer between upper and lower DC link.
Despite the benefits of interleaving when compared with the single converter case, there are certainly some disadvantages of using this topology. For example, this topology would likely require more volume when compared to the single converter case due to the additional devices, necessary gate driver components, and additional magnetics. For these reasons, this topology was evaluated not as a direct competition to the single converter case, but as a necessary extension of that topology if the single converter was not able to provide the necessary rated power to support the UPS. Due to the nature of this topology, its switching sequences and basic operation will not be discussed as this converter is simply an interleaved extension of the three-level topology discussed previously.
Common-Mode Voltage Simulations and Waveforms
In order to determine which converters, if any, provided some benefit in terms of common-mode voltage emissions, it was necessary to simulate the converters to capture their common-mode voltage profiles. To do this, each converter topology was simulated under ideal conditions using the PLECS plugin for MATLAB Simulink. Each converter was simulated under standard operating conditions, as well as with a phase-shifted operation to reduce output current ripple if applicable. In each simulation, the total DC link was 800 V and consisted of two 400 V ideal DC sources in series. The output voltage was set at a nominal voltage of 540 V. Waveforms of each type of operation for the various converters are shown.
As demonstrated in the preceding waveforms, the common-mode voltage output of the converters is as expected. The buck converter has a CMV pulse of -400 V which corresponds to the common-mode voltage of the converter while freewheeling. Also, those converters which are able to operate in the symmetrical synchronous switching manner described previously do not produce any common-mode voltage under ideal conditions.
Also, in the phase-shifted operation, some similarities and differences are noted. Recall that this kind of operation is typically used to halve the output current ripple to reduce the output filter components. As the simple buck converter is not capable of such operation, it is excluded from these results. When the converters operate in such a fashion, there is some common-mode voltage generated which corresponds to switching states where power is transferred asymmetrically from only one of the DC link potentials. Although there are more non-zero pulses when compared to the simple buck converter, the magnitude of these pulses is only 200 V, meaning that the overall impact of this operation on the UPs is expected to be similar to that of the buck converter.
At this point, the PEBB-based topology was no longer considered. This is because the additional switching states and functionality of the converter are not utilized due to the fixed polarity of the battery. If the battery voltage were to somehow fluctuate in sign as well as magnitude, this topology would be considerably more useful. As it stands, however, it is simply a costlier, less effective version of the three-level buck converter
Efficiency Simulations and Comparison
Once the benefits and drawbacks of each topology’s impact on the UPS noise profile were better understood, it was necessary to evaluate the efficiency of each topology to determine if achieving 99% efficiency would be possible with each topology. Also, if there were any significant concerns regarding the efficiency of a specific topology, those would be better understood through simulation. To simulate the efficiency, datasheet loss values were used for devices, and the converters were assembled in PLECS. The datasheet information was taken from the Microsemi APTMC60TLM55CT3AG inverter datasheet. This is the module which was selected for the inverter and rectifier stages of the UPS, so it was expected that the DC/DC stage of the UPS would use something similar. The junction temperature of the devices was kept constant using a heatsink directly attached to an ambient temperature of 50 °C. A picture of the simulation setup is shown.
Chapter 1. Introduction
1.2. Thesis Outline
Chapter 2. Topology Comparison and Evaluation
2.1. Project Requirements and Converter Specifications
2.2. Buck Converter
2.3. Three-Level Buck Converter
2.4. PEBB-Based Converter
2.5. Interleaved Three-Level Buck Converter
2.6. Efficiency Simulations and Comparison
2.7. UPS Noise Profile Comparison with Three-Terminal Model
Chapter 3. Converter Modeling and Simulation
3.1 Converter Average and Small Signal Model
3.2. Model Verification with Simulation
Chapter 4. Hardware Design and Construction
4.1. Loss Extraction and Double Pulse Tests
4.2. Updated Simulation with Extracted Losses
4.3. Hardware Assembly
Chapter 5. Experimental Results
5.1. DC/DC Open Loop Testing and Efficiency Measurement
5.2. DC/DC Closed Loop Testing
Chapter 6. Conclusions and Future Work
6.1. Summary and Final Thoughts
6.2. Future Work
GET THE COMPLETE PROJECT
Modeling and Design of a SiC Zero Common-Mode Voltage Three-Level DC/DC Converter