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Table of contents
Chapter 1 Introduction
1.1 Background
1.1.1 Design Time Application Mapping
1.1.2 Platform Architecture Exploration
1.1.3 Run-time Platform Management
Chapter 2 MPSoC Programming Model
2.1 ADRES
2.1.1 ADRES Architecture
2.2 Memory Hierarchy
2.2.1 Scratch Pad Memories
2.2.2 THE MH TOOL
2.2.2.1 Data-reuse analysis
2.2.2.2 Optimization
2.3 The Run-time Manager
2.3.1 Quality Manager
2.3.2 Resource Manager
2.3.3 Run-Time Library
2.4 Clean C
2.5 ATOMIUM / ANALYSIS (ANL)
2.5.1 Atomium/Analysis Process Flow
2.6 MPA TOOL
2.7 High Level Simulator (HLSIM)
Chapter 3 Previous Work
3.1 Experimental workflow and code preparation
3.2 MPEG-4 Encoder Experiment
3.3 Platform Template
Chapter 4 Methodology & Implementation
4.1 ANL Profiling for Sequential MPEG-4 Encoder
4.1.1 Preparing the program for ATOMIUM
4.1.2 Instrumenting the program using ATOMIUM
4.1.3 Compiling and Linking the Instrumented program
4.1.4 Generating an Access count report
4.1.5 Interpreting results
4.2 Discussion on Previous Parallelizations
4.3 Choosing optimal parallelizations for run-time switching
4.4 Run-time parallelization switcher
4.4.1 Configuring new component
4.4.2 Switching decision spot
4.4.3 Manual adjustment to code and tools
4.4.3.1 Adding new threads and naming convention
4.4.3.2 Parsection switching & parallelization spawning
4.4.3.3 Replicating and Adjusting functionalities called by threads
4.4.3.4 Adjusting ARP instrumentation
4.4.3.5 Updating platform information
4.4.3.6 Block Transfers and FIFO communication
4.4.3.7 Execution and Profiling
Chapter 5 Results
5.1 Interpreting ANL profiling results
5.2 Profiling Parallelization switcher component
5.3 The Final Pareto Curve
Chapter 6 Conclusions and Future Work
6.1 Conclusions
6.2 Future Work
REFERENCES
