Alternate Bitcell Architecture

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Table of contents

1 General Introduction 
2 Variability in Ultra-Deep-Submicron CMOS 
2.1 Introduction to Variability
2.2 Variability Sources in CMOS
2.2.0.1 Systematic Variability
2.2.0.2 Random Variability
2.2.0.3 Time Dependency in Variability
2.3 The Improvement Techniques for Variability and New Device Architectures
2.4 Conclusion
3 The Impact of the Variability in Static Random Access Mem-ory 
3.1 Introduction to SRAMs limitations in modern System-On-Chips
3.2 SRAM Bitcell Architecture and Common Operations
3.3 Alternate Bitcell Architecture
3.4 A Simple Model for the Bitcell Variability Space
3.5 SRAM Bitcell Failure Analysis
3.5.1 SRAM Bitcell Static (DC) Analysis
3.5.1.1 Static Noise Margin
3.5.1.2 Write Margin
3.5.2 SRAM Bitcell Dynamic Analysis
3.5.2.1 Read-Ability
3.5.2.2 Write-Ability
3.5.2.3 Multiple-Pulse Analysis and Figure of Merits
3.6 6T-SRAM Bitcell Failure Mechanisms
3.7 The Minimum Operating Voltage Vmin
4 SRAM Bitcell Variability Space Modeling for Vmin Estima-tion 
4.1 Bitcell Variability Space Modeling using Monte Carlo SPICE simulations
4.2 SRAM Static Vmin Analysis
4.2.1 6T Bitcells Static Vmin Measurements and SPICE Mod-eling Results
4.2.2 Ultra-Low-Voltage SRAM Static Vmin Measurements and Modeling Results
4.3 Bitcell Variability Space Modeling using Smart Algorithm : Hypersphere Most Probable Failure Point Search Methodology
4.3.1 Bitcell Failure Probability Calculation
4.4 SRAM Dynamic Vmin Analysis
4.4.1 Bitcell Dynamic Fail/Pass SPICE Analysis using Hy-persphere Algorithm
4.4.1.1 Read-Ability Test
4.4.1.2 Write-Ability Test
4.4.1.3 Read-After-Write Test
4.4.2 SRAM Dynamic Failures on Silicon
4.5 Application Example: Hypersphere MPFP Search for Inves-tigations on SNM Yield Loss at High-Voltage in 28nm UTBB FD-SOI SRAM bitcells
4.6 Smart Dynamic Back-Biasing Bitcell Vmin Boost in UTBB FD-SOI
4.7 Conclusion
5 Random Telegraph Signal Noise in 28nm UTBB FD-SOI and the impact on 6T SRAM 
5.1 Time-Dependent Random Telegraph Signal Noise Variability
5.2 SPICE-level RTS Noise Modeling in UTBB FD-SOI
5.2.1 RTS Trap Characteristics and Particularity of UTBB FD-SOI
5.2.2 Front- and Back-gate Coupling Aware 2-Dirac Charge Inversion model
5.2.3 RTS-aware 6T SRAM SPICE netlist generation in Matlab
5.3 Measurements and Simulation Results
5.3.1 Hardware Setup
5.3.2 Results
5.4 Conclusion
6 General Conclusion 
6.1 Key Contributions
6.2 Future Work