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Table of contents
1 Introduction
1.1 Terminology
1.2 Hardware System Security
1.3 Notations and Conventions
1.4 Finite Fields Arithmetic
1.5 Thesis Outline
1.6 Publications
2 From a Transistor to a Cryptosystem
2.1 Integrated Circuit and Logic Design
2.1.1 Introduction
2.1.2 VLSI Design
2.1.3 The CMOS Transistor
2.1.4 CMOS Logic
2.1.4.1 The Inverter
2.1.4.2 The NAND Gate
2.1.4.3 Compound Gates
2.1.4.4 Tri-state Buffers
2.1.5 CMOS I-V Characteristics
2.1.5.1 CMOS Electrical Properties
2.1.5.2 Non-Ideal I-V Effects
2.2 Hardware-Based Cryptosystems
2.2.1 Introduction
2.2.2 Definitions
2.2.3 Hardware Design Architecture
2.2.3.1 Throughput and Latency
2.2.3.2 Area
2.2.4 Cryptographic Hardware Design
2.2.4.1 Iterative Looping
2.2.4.2 Loop Unrolling
2.2.4.3 Pipelining
2.2.4.4 Sub-Pipelining
2.2.4.5 Pseudo-Random Sequences in Hardware
2.3 Private-Key Cryptosystems
2.3.1 The Data Encryption Standard
2.3.2 The Advanced Encryption Standard
2.3.2.1 AES Rounds
2.3.2.2 AES in Hardware (FPGA and ASIC)
2.4 Cryptographic Hash Functions
2.4.1 Introduction
2.4.2 Security Requirements of Hash Functions
2.4.2.1 Preimage Resistance
2.4.2.2 Second Preimage Resistance
2.4.2.3 Collision Resistance
2.4.2.4 Overview of Hash Algorithms
2.4.3 The Secure Hash Algorithm 1
2.4.4 The Secure Hash Algorithm 2
2.4.5 Implementation Tradeoffs and Design Methodologies
2.4.6 Known SHA-2 Hardware Optimization Techniques
2.4.7 FPGA-Based Cryptography
2.4.8 SHA-2 in Hardware (FPGA and ASIC)
3 Cryptographic Hardware Acceleration and Power Minimization
3.1 BCH with Barrett Polynomial Reduction
3.1.1 Introduction
3.1.2 Barrett’s Reduction Algorithm
3.1.2.1 Dynamic Constant Scaling
3.1.3 Barrett’s Algorithm for Polynomials
3.1.3.1 Orders
3.1.3.2 Terminology
3.1.3.3 Polynomial Barrett Complexity
3.1.3.4 Barrett’s Algorithm for Multivariate Polynomials
3.1.3.5 Dynamic Constant Scaling in Q[⃗x]
3.1.4 Application to BCH Codes
3.1.4.1 General Remarks
3.1.4.2 BCH Preliminaries
3.1.4.3 BCH Decoding
3.1.4.4 Syndrome
3.1.4.5 Error Location
3.1.4.6 Peterson’s Algorithm
3.1.4.7 Chien’s Error Search
3.1.5 Implementation and Results
3.1.5.1 Standard Architecture
3.1.5.2 LFSR and Improved LFSR Architectures
3.1.5.3 Barrett Architecture (regular and pipelined)
3.1.5.4 Performance
3.2 Managing Energy on SoCs and Embedded Systems
3.2.1 Introduction
3.2.2 The Model
3.2.3 Optimizing Power Consumption While Avoiding System Malfunction
3.2.4 The General Case
3.2.5 Probabilistic Strategies
4 Side-Channel Attacks and Hardware Countermeasures
4.1 An Economical Introduction to Side-Channel Attacks
4.2 Differential Cryptanalysis
4.3 Differential Power Analysis
4.4 Power Scrambling and the Reconfigurable AES
4.4.1 Introduction
4.4.2 The Proposed AES Design
4.4.3 Energy and Security
4.4.3.1 Power Analysis
4.4.3.2 Power Scrambling
4.4.3.3 Transient Fault Detection
4.4.3.4 Permanent Fault Detection
4.4.3.5 Runtime Configurability
4.4.4 Halving the Memory Required for AES Decryption
4.4.5 Implementation Results
4.5 Cryptographically Secure On-Chip Firewalling
4.5.1 Introduction
4.5.2 Identifying Attack Surfaces on NoCs
4.5.2.1 Request Path
4.5.2.2 Firewall Reprogramming Path
4.5.2.3 Firewall State at Rest
4.5.3 Integration of Security Resources into an SoC
4.5.3.1 Securing the Request Path
4.5.3.2 Securing the Firewall
4.5.4 Access Control Firewalling to On-Chip Resources
4.5.4.1 Endpoint versus NoC Firewalling
4.5.4.2 Cryptographically Secure Access Control
4.5.4.3 CSAC Synthesis Results
4.5.4.4 FPGA Implementation
4.6 Practical Instantaneous Frequency Analysis Experiments
4.6.1 Introduction
4.6.2 Preliminaries
4.6.2.1 The Hilbert Huang Transform
4.6.2.2 AES Hardware Implementation
4.6.3 Hilbert Huang Transform and Frequency Leakage
4.6.3.1 Why Should Instantaneous Frequency Variations Leak Information?
4.6.3.2 Power consumption of one AES round
4.6.3.3 Hilbert Huang Transform of an AES Power Consumption Signal
4.6.4 Correlation Instantaneous Frequency Analysis
4.6.4.1 Correlation Instantaneous Frequency Analysis on Unprotected Hardware
4.6.4.2 Correlation Instantaneous Frequency Analysis in the Presence of DVS 5 Zero-Knowledge Protocols and Authenticated Encryption
5.1 Public-Key Based Lightweight Swarm Authentication
5.1.1 Introduction
5.1.2 Preliminaries
5.1.2.1 Fiat-Shamir Authentication Protocol
5.1.2.2 Topology-Aware Distributed Spanning Trees
5.1.3 Distributed Fiat-Shamir Authentication
5.1.3.1 The Approach
5.1.3.2 Back-up Authentication
5.1.4 Security
5.1.4.1 Soundness
5.1.4.2 Zero-knowledge
5.1.4.3 Security Analysis
5.2 The Offset Merkle-Damgård Authenticated Cipher
5.2.1 Introduction
5.2.2 Preliminaries
5.2.2.1 Security Definitions and Goals
5.2.2.2 Quantitative Security Level of OMD-SHA256
5.2.2.3 Quantitative Security Level of OMD-SHA512
5.2.2.4 Security Proofs
5.2.2.5 Generalization of OMD Based on Tweakable Random Functions
5.2.2.6 Instantiating Tweakable RFs with PRFs
5.2.3 Specification of OMD
5.2.3.1 The OMD Mode of Operation
5.2.3.2 OMD-SHA256: Primary Recommendation for Instantiating OMD
5.2.3.3 OMD-SHA512: Secondary Recommendation for Instantiating OMD
5.2.3.4 Compression Functions of SHA-256 and SHA-512
6 Conclusion
A Code: Barrett’s Algorithm for Polynomials
B Compression Functions
B.1 Compression Functions of SHA-256 and SHA-512
B.1.1 The Compression Function of SHA-256
B.1.2 The Compression Function of SHA-512
