(Downloads - 0)
For more info about our services contact : help@bestpfe.com
Table of contents
CHAPTER I TRANSISTOR MOSFET: THEORY, CHARACTERIZATION AND MISMATCH CONCEPT
I.1 MOSFET transistor
I.1.1 Operation principle
I.1.2 Electrical figures of merits for static performance
I.1.3 Operating Regimes
I.1.4 Parasitic effects due to the Miniaturization of MOS transistors
I.2 Methodology of extraction of MOS transistors parameters
I.2.1 Maximum slope method
I.2.2 Constant current method
I.2.3 Y function method
I.3 Types of electrical variability
I.4 Local variability
I.4.1 Measurement phase
I.4.2 Gaussian distribution verification
I.4.2.a Data plot
I.4.2.b Gaussian law verification
I.4.3 Data filtering and separation between systematic and stochastic mismatch
I.4.4 Concept and computation of systematic mismatch
I.4.4.a Concept of systematic mismatch
I.4.4.b Systematic mismatch computation
I.4.4.c Confidence interval
I.4.5 Stochastic mismatch
I.4.5.a Concept and computation of stochastic mismatch
I.4.5.b Confidence interval
I.4.5.c Deviations from Pelgrom‟s Law
I.5 Mismatch measurement system and test structures
I.5.1 Mismatch measurement system
I.5.2 Mismatch test structures
I.6 Stochastic mismatch contributions and effects in Bulk technology: state of the art.
I.7 Improvements due to FD SOI technology
I.7.1 Main advantages of SOI over BULK technology
I.7.2 Stochastic mismatch contributions and effects in FD SOI technology: State of the art
I.8 Conclusions
CHAPTER II NEW METHOD FOR THE EXTRACTION OF THE THRESHOLD VOLTAGE AND CURRENT GAIN FACTOR MISMATCH AND NEW DRAIN CURRENT MISMATCH MODEL
II.1 Introduction and motivation of this work
II.2 New Y-function based mismatch extraction method (strong inversion regime)
II.3 New drain current mismatch model
II.3.1 Validation of the new drain current mismatch model
II.4 Experimental Results
II.4.1 Experimental setup
II.4.2 FD SOI NMOS transistors of moderate gate length (W=1μm/L=0.1μm)
II.4.3 FD SOI NMOS transistors with short gate length (W=0.08μm/L=0.05μm)
II.4.4 Bulk NMOS transistors with short gate length (W=10μm/L=0.03μm)
II.5 Conclusions
CHAPTER III CASCODE CONFIGURATION AS A SUBSTITUTE TO LDE MOSFET FOR IMPROVED ELECTRICAL MISMATCH PERFORMANCE
III.1 Introduction and motivation of this work
III.2 Experimental details
III.3 Vt, β and ID mismatches comparison for LDEMOS, Individual and cascode configuration device
III.3.1 Linear Regime
III.3.1.a Vt and β mismatch
III.3.1.b ID mismatch
III.3.2 Saturation Regime
III.3.2.a Vt mismatch
III.3.2.b ID mismatch
III.4 Conclusions and perspectives
CHAPTER IV IMPACT OF GE PROPORTIONS IN P-MOSFET CHANNEL ON MATCHING PERFORMANCES IN 28NM GATE FIRST BULK TECHNOLOGY
IV.1 Introduction (State of the art)
IV.2 Experimental setup
IV.3 Electrical parameters mismatch characterization on transistors without pocket implants
IV.3.1 Threshold Voltage mismatch
IV.3.2 Current gain factor mismatch
IV.3.3 Drain current mismatch
IV.4 Electrical parameters mismatch characterization on transistors with heavily pocket implants
IV.4.1 Threshold Voltage mismatch
IV.4.2 Current gain factor mismatch
IV.4.3 Drain current mismatch
IV.5 Conclusions
CHAPTER V MISMATCH CHARACTERIZATION OF 20NM GATE-LAST BULK CMOS TECHNOLOGY
V.1 Introduction (State of the art)
V.2 Experimental details
V.3 Comparison of devices with channel pocket implants and different oxide thicknesses EOT (Tox) in 20nm Gate-Last technology
V.3.1 Threshold Voltage mismatch
V.3.2 Current gain factor mismatch
V.3.3 Drain Current mismatch
V.4 Comparison between 28nm Gate-first and 20 nm Gate-last Bulk technologies
V.4.1 Threshold Voltage mismatch
V.4.2 Current gain factor mismatch
V.5 Vt and β mismatch trends as a function of Tox
V.6 Conclusions
CHAPTER VI MISMATCH BEHAVIOR IN ADVANCED FD SOI CMOS TECHNOLOGIES
VI.1 Introduction
VI.2 Mismatch behavior in 14nm and 28 nm FD SOI CMOS technology
VI.2.1 Experimental details
VI.2.2 Effect of EOT: Comparison between GO1 and GO2 for 14nm FD SOI technology
VI.2.2.a Threshold Voltage mismatch
VI.2.2.b Current gain factor mismatch
VI.2.3.c Drain current mismatch
VI.2.3 Comparison between 28nm and 14 nm FD SOI technologies
VI.2.3.a Threshold Voltage mismatch
VI.2.3.b Current gain factor mismatch
VI.2.4.c Drain current mismatch
VI.2.4 FD SOI technology mismatch summary and discussions
VI.3 Mismatch behavior with transistor aging in response to NBTI stress
VI.3.1 Brief description of NBTI Stress
VI.3.2 Experimental details
VI.3.3 Mismatch behavior in response to NBTI stress for GO1 and GO2 28nm FD SOI devices
VI.3.3.a Experimental results
VI.3.3.b Theoretical models and discussions
VI.4 Conclusions
GENERAL CONCLUSIONS AND PERSPECTIVES
AUTHOR PUBLICATIONS
