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Table of contents
Chapter 1. Electrostatic doping: The concept and related devices
1.1. Introduction
1.2. Electrostatic doping
1.3. Why electrostatic doping?
1.3.1. Semiconductor technology
1.3.2. Electrostatic doping in FD-SOI technology
1.4. Emerging material devices with electrostatic doping
1.4.1. Carbon nanotube
1.4.2. Graphene
1.4.3. Silicon (Si) nanowires
1.4.4. Two Dimensional (2D) materials
1.5. FD-SOI devices with electrostatic doping
1.5.1. Tunneling Field Effect Transistor (TFET)
1.5.2. Lateral Double-diffused Metal Oxide Silicon (LDMOS)
1.5.3. Impact ionization Metal Oxide Silicon (IMOS)
1.5.4. Gated Diode merged NMOS (GDNMOS)
1.5.5. Charge Plasma Diode
1.5.6. Bipolar Charge Plasma Transistor
1.6. Conclusion
1.7. References
Chapter 2. The Hocus-Pocus diode: Fabrication, device operation and applications
2.1. Introduction
2.2. The Hocus-Pocus (HP) diode
2.2.1 Device fabrication
2.2.2 Principle of operation
2.3. The virtual P-N diode
2.3.1. Reverse current characteristics
2.3.2. Forward current characteristics
2.3.3. TCAD Simulation
2.3.4. Asymmetric characteristics
2.3.5. Semi-virtual P-N diode
2.3.6. Esaki diode characteristics
2.4. The virtual P-I-N diode
2.4.1. Characteristics
2.5 Other metamorphosis in HP diode
2.5.1 TFET and Z2-FET
2.6. Lifetime extraction in ultrathin film
2.6.1. Lifetime extraction methods
2.6.1.1. Deep depletion technique
2.6.1.2. Photo-conductance decay technique
2.6.2. Lifetime extraction method using HP diode
2.6.2.1. Forward I-V characteristic
2.6.2.2. Recombination and diffusion current
2.6.2.3. Reverse Recovery Transient (RRT) Method
2.6.2.3.1. The virtual P-N diode
2.6.2.3.2. The virtual P-I-N diode
2.6.2.4 Double gated P-I-N diode
2.7. Conclusion
2.8. References
Chapter 3. Z2-FET: capacitorless 1T-DRAM and logic switch
3.1. Introduction
3.2. Physics in capacitorless 1T-DRAM Z2-FET operation
3.2.1. DC operation
3.2.2. Transition between DC and pulse mode
3.2.3. Transient characteristics
3.3. Experimental validation of Z2-FET memory operation
3.3.1. DC operation
3.3.2. Transient mode operation
3.3.2.1. Standard memory operation
3.3.2.2. Retention
3.3.2.3. High temperature measurement
3.4. Advanced Z2-FET memory
3.4.1. Advanced Z2-FET structure: dual ground-plane
3.4.2. Selection-transistor-free Z2-FET memory array
3.5. Z2-FET as a logic switch
3.5.1. Z2-FET with single ground-plane
3.5.2. Novel Z2-FET with dual ground-plane
3.6. Conclusion
3.7. References
Conclusion and perspectives
