High−k and Metal gate (HKMG)

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Table of contents

Chapter 1 Context of the work
1.1 The context of CMOS technology
1.1.1 CMOS scaling down and Short channel effects
1.2 Advanced CMOS technology
1.3 Devices under study
1.4. Dissertation scope and outline
Chapter 2 Theoretical and experimental backgrounds
2.1 Parameter extraction methods for MOSFETs
2.1.1 Mobility
2.1.2 Series Resistance from the Y−function method
2.1.3 Threshold voltage (VT)
2.1.4 Subthreshold swing (SS)
2.2 Magnetoresistance
2.2.1 Principle of magnetoresistance mobility extraction
β.β.β Comparison between 􀈝eff, 􀈝H and 􀈝MR
2.3 Low frequency noise
2.3.1 Fundamental noise sources
Chapter 3 Full split C−V method for parameter extractions
3.1 Introduction
3.2 Experiment details
3.3 Results and Discussions
3.3.1 Refinement of gate−to−channel capacitance analysis
3.3.2 Gate−to−bulk capacitance exploitation in UTBB FDSOI
3.4 Conclusions
Chapter 4 In depth characterization of carrier transport in 14nm FD−SOI CMOS transistors
4.1 Introduction
4.2 Experiment details
4.3 Results and Discussions
4.3.1 General transport characteristics of NMOS devices and methodologies
4.3.2 Transport properties of PMOS devices
4.4 Conclusions
Chapter 5 Low temperature characterization of mobility in 14nm FD−SOI CMOS devices under interface coupling conditions
5.1 Introduction
5.2 Experiment details
5.3 Results and Discussions
5.3.1 Long channel
5.3.2 Gate−length variations
5.3.2 Short channel in interface coupling conditions
5.4 Conclusions
Chapter 6 Magnetoresistance mobility characterization in advanced FD−SOI transistors
6.1 Characterization of magnetoresistance in linear regime of FD−SOI nMOS devices
6.1.1 Introduction
6.1.2 Experiment details
6.1.3 Results and discussions
6.1.3.1 μMR extraction in long channel at 300K
6.1.3.2 Influence of temperature and gate length variations
6.1.3.3 Additional mobility induced by high−k layer
6.1.3.4 Mobility degradation factor
6.1.4 Conclusions
6.2 Experimental and theoretical investigation of magnetoresistance from linear to saturation regime in 14−nm FD−SOI MOS devices
6.2.1 Introduction
6.2.2 Experiment details
6.2.3 Physical compact model of high field transport with magnetoresistance effect
6.2.4 Results and discussions
6.2.4.1 μMR extraction procedure
6.2.4.2 Modeling of I−V and 􀈝MR in all operation regimes
6.2.4.3 Carrier velocity extraction
6.2.4.4 Comparative analysis of carrier velocity
6.2.5 Conclusions
Chapter 7 Low−frequency noise characterization of 14nm−node FD−SOI CMOS transistors
7.1 Introduction
7.2 Experiment details
7.3 Results and Discussions
7.3.1 Noise characterization in the linear regime
7.3.2 Noise characterization from the linear to saturation regime
7.4 Conclusions
Chapter 8 Conclusions