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Table of contents
General introduction
Context
Thesis objectives and outline
1. Gate stack technology for 14/28 nm FDSOI MOSFET devices
1.1 MOSFET device
1.1.1 MOSFET operation
1.1.2 Metal-Oxide-Semiconductor gate stack properties
1.2 Gate stack fabrication process
1.2.1 Gate dielectrics
1.2.2 Metal gate electrode and deposition techniques
1.2.3 Metal gate integration in 14 nm Fully-Depleted SOI devices
1.2.4 Introduction of additives for workfunction engineering
1.3 Process flow
1.3.1 MOS transistor Process flow
1.3.2 Process flow simplification for MOS capacitor
1.3.3 Beveled Interlayer Oxide
1.4 MGG induced VT variability
1.5 MOSFET reliability
1.5.1 Bias temperature instability (BTI)
1.5.2 Time dependent oxide breakdown (TDDB)
1.6 Conclusion
2. Characterization techniques for the gate stack
2.1 Electrical characterization
2.1.1 CV measurements and electrical parameters extraction
2.1.2 Sheet resistance measurements by four probe method
2.2 Physicochemical and Stress characterization
2.2.1 X-ray Photoelectron Spectroscopy (XPS)
2.2.2 X-Ray Fluorescence (XRF)
2.2.3 X-Ray Diffraction (XRD)
2.2.4 Mechanical stress measurements
2.3 Conclusion
3. Impact of La and Al additives on MOSFET reliability
3.1 Impact of La and Al additives on BTI reliability
3.1.1 Device fabrication
3.1.2 Electrical measurements and analysis
3.1.3 Results
3.2 Impact of La and Al additives on TDDB reliability
3.2.1 Electrical measurements
3.2.2 Results
3.3 Conclusion
4. Impact of TiN process on its microstructure and electrical properties
4.1 Context
4.2 Device fabrication
4.3 Measurements and results
4.3.1 In-plane XRD for TiN grain size
4.3.2 θ-2θ XRD for TiN grain orientation
4.3.3 Mechanical stress
4.3.4 Resistivity of TiN films
4.3.5 Effective workfunction measurements
4.3.6 Grain size variation with wafer radius
4.3.7 Effect of substrate temperature
4.3.8 TiN grain analysis by ASTAR technique
Conclusion
5. Study of La and Al diffusion in HKMG stack
5.1 Introduction to diffusion
5.2 Device fabrication
5.3 Results
5.3.1 Modulation of diffused additive dose by DIA conditions
5.3.2 Modulation of effective workfunction by DIA conditions
Conclusion
6. X-ray Photoelectron Spectroscopy under bias
6.1 State of the art and the need for XPS under bias
6.2 Test structures and their biasing issues
6.2.1 Test structures and their process flow
6.2.2 Biasing issues in the test structures
6.2.3 Biasing solutions and electrical modelling
6.3 Issues related to the XPS equipment
6.3.1 Device location
6.3.2 XPS beam position error and size estimation
6.3.3 Impact of X-ray beam on the gate stack
6.3.4 Reduction of substrate resistance
6.4 XPS under bias technique validation
6.4.1 XPS spectra fitting methodology
6.4.2 Shift of binding energies with bias
6.4.3 Technique validation
6.5 Dipole localization by XPS under bias
6.5.1 Dipoles related to La and Al addition
6.5.2 Methodology to reduce experimental difficulties
6.2.3 Dipoles related to TiN thickness modulation
Conclusion
Conclusions and perspectives
List of publications
List of Patents
Annex
