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Table of contents
Chapter 1: Introduction
1.1 MOSFET downscaling and evolution
1.2 SOI Technology
1.2.1 Introduction to SOI
1.2.2 SOI Wafers and CMOS SOI Process Technologies
1.2.3 SOI MOSFET Physics
1.2.4 SOI MOSFET Characterization
1.2.5 UTBB FD-SOI Process
1.3 Electrostatic Discharges (ESD)
1.3.1 Generation mechanisms and ESD stress models
1.3.2 Protection devices and protection strategies
1.3.3 ESD Characterization Methods
References
Chapter 2: BiMOS device
2.1 DC operation
2.1.1 Principle of operation
2.1.2 Fabrication process
2.1.2.1 pMOS contact
2.1.2.2 Fork-gate contact
2.1.3 Physical mechanisms
2.1.4 DC measurements
2.1.4.1 MOSFET mode of operation
2.1.4.2 Hybrid mode of operation
2.1.5 TCAD simulations
2.1.5.1 Subthreshold operation and barrier modulation
2.1.5.2 Base current
2.1.6 Low temperature measurements
2.2 ESD protection operation
2.2.1 Principle of operation
2.2.2 Isothermal high current TCAD simulations and physical mechanisms
2.2.3 Electro-thermal high current TCAD simulations and physical mechanisms
2.2.4 Carrier mobility effect on high current TCAD simulations
2.2.5 ESD measurements and DC leakage measurements
2.3 Other modes of BiMOS operation
2.3.1 Amplification element
2.4 Conclusions
References
Chapter 3: GDNMOS device
3.1 Thyristors / SCRs
3.2 Physical Mechanisms
3.3 Fabrication Process
3.4 TCAD simulations
3.4.1 Isothermal Simulations
3.4.2 Electrothermal Simulations
3.5 DC measurements
3.6 ESD measurements
3.6 Thyristor behavior through doping modification
3.7 Conclusions
References
Chapter 4: Four-gate transistor (G4-FET)
4.1 Structure and principle of operation
4.2 Model
4.3 Fabrication process
4.4 TCAD simulations
4.5 DC measurements
4.6 A fundamental application of G4-FET: Evidence of supercoupling effect
4.7 4-Gate JFET mode of BiMOS structure
4.8 Conclusions
References
Chapter 5: Band-to-Band BJT
5.1 Band-to-band tunneling effect and TFETs
5.2 Tunneling FETs on standard 28nm FD-SOI technology
5.2.1 TCAD simulations
5.2.2 TFET fabrication
5.2.3 TFET measurements
5.2.3.1 Characterization : ID(VG) for VBP=0V for P#1
5.2.3.2 Characterization : ID(VG) for VBP=±5V for P#1
5.2.3.3 Characterization : ID(VG) for different VBP values and for P#2
5.2.3.4 Characterization : ID(VD) curves for P#1
5.2.3.5 ESD behavior: TLP characterization
5.3 Tunneling FETs on standard 14nm FD-SOI technology
5.4 BET-FET devices
5.5 Band-to-band bipolar junction transistor
5.5.1 Structure and operating principle
5.5.2 TCAD Simulations
5.5.2.1 Behavior through ‘Gummel’ plots
5.5.2.2 Recombination rates and the role of STI
5.5.2.3 Base resistance (RB) modulation
5.5.2.4 Tunneling resistance (RT) modulation
5.5.2.5 Behavior through gate biasing modulation
5.5.3 B2BJT Fabrication
5.5.4 B2BJT Measurements
5.6 Conclusions
References
Chapter 6: Conclusions and perspectives
6.1 Conclusion
6.2 Future perspectives
References
