T-DRAM in Fully Depleted Silicon on Insulator (FDSOI) Technology

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Table of contents

Chapter 1. Sharp-Switching Devices: State of the Art and Applications
1.1. Introduction
1.2. MOSFET Transistor: State of Art and Trends
1.3. Migration to FDSOI
1.3.1. SOI Technology
1.3.2. MOS Transistor in UTBB FDSOI Technology
1.4. Sharp-Switching Devices
1.4.1. Tunnel Field Effect Transistor (TFET)
1.4.2. Ferroelectric FET
1.4.3. Nano-electro-mechanical FET
1.4.4. NEM Relay
1.4.5. I-MOS: Impact Ionization MOSFET
1.4.6. Band-Modulation Devices: Operation Principle and Variants
1.5. Electrostatic Discharge (ESD)
1.5.1. Context and Physical Mechanism
1.5.2. ESD-Induced Failure in Integrated Circuits
1.5.3. ESD Stress Models
1.5.4. Protection Methods
1.5.5. Characterization Methods
1.6. 1T-DRAM: Capacitorless Dynamic Random Access Memory
1.6.1. Introduction
1.6.2. Motivations and State of the Art
1.6.3. 1T-DRAM in Partially Depleted SOI and Bulk Technologies
1.6.4. 1T-DRAM in Fully Depleted Silicon on Insulator (FDSOI) Technology
1.7. Conclusion
1.8. References
Chapter 2. Band-Modulation Devices: Fabrication Process and Operation Principle
2.1. Introduction
2.2. Zero Subthreshold Slope and Zero Impact Ionization FET: Standard Z2-FET
2.2.1. Device Fabrication
2.2.2. Principle of Operation
2.3. Novel Band-Modulation Device with Dual Ground Planes: Z2-FET DGP
2.3.1. Device Architecture
2.3.2. Advantage of Dual GP
2.4. Back-Gate Modulated Device with No Front-Gate : Z3-FET
2.4.1. Fabrication Process
2.4.2. Advantage of No Front-Gate
2.5. Conclusion
2.6. References
Chapter 3. Measurement and Modeling of Z-FET Family Devices
3.1. Introduction
3.2. DC Measurements
3.2.1. Impact of Silicon Thickness on Z-FET Devices Behavior
3.2.2. Impact of Z-FET Devices Parameters
3.2.3. FDSOI 28 nm node vs. 14 nm node
3.3. TLP Measurements
3.3.1. Standard Z2-FET
3.3.2. Z3-FET
3.3.3. Stacked Architectures
3.4. Interface Potential Analytical Model
3.4.1. Introduction
3.4.2. Potential Distribution Model
3.4.3. Model Verification
3.4.4. Z2-FET DGP and Z3-FET
3.5. Conclusion
3.6. References
Chapter 4. Z-FET Devices as 1T-DRAM and Logic Switch
4.1. Introduction
4.2. Capacitor-less Dynamic Random Access Memory: 1T-DRAM Application
4.2.1. Operation Principle
4.2.2. Memory Operation Analysis via TCAD Simulation
4.2.3. Measurement Bench
4.2.4. Transient Experimental Results
4.2.5. Z2-FET Memory Cell in a Matrix
4.3. Z2-FET DGP as a Logic Switch in 14 nm node
4.3.1. Transient Experimental Results
4.4. Conclusion
4.5. References
Conclusion and Perspectives