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Table of contents
1. Need of 3D-channels in CMOS technology
1.1. Physics of multi-gate devices: scaling length volume inversion & mobility.
1.1.1. CMOS scaling.
1.1.2. Double gate device physics: volume inversion
1.1.3. Multi-gate device physics: carrier transport in thin films.
1.1.4. Conclusion
1.2. Double-gate devices: from FDSOI and FinFET to nanowires
1.2.1. FDSOI
1.2.2. Horizontal Double-gate devices
1.2.3. Silicon-On-Nothing (SON)
1.2.4. Vertical double-gate: towards FinFET
1.2.5. Conclusions
1.3. The nanowire technology: down to the end of the roadmap?
1.3.1. Tri-Gates, π-gate, Ω-gate and gate-all-around (GAA) nanowire FETs
1.3.2. Technology boosters: channel orientation and strain in trigate nanowire FETs.
1.3.3. Technology boosters: the case of Sidewall Image Transfer (SIT)
1.3.4. Stacked NWs
1.3.5. Conclusion and thesis proposal
2. Benchmarking Stacked Nanowires Technologies with FinFET
2.1. TCAD Model: Simulation Parameters and Extraction
2.1.1. TCAD model
2.1.2. Intrinsic delay approximation
2.1.3. Parasitic capacitances – inverter equivalent capacitance
2.2. Electrostatics of 3D-architectures
2.2.1. Subthreshold behavior
2.2.2. Parasitic capacitances
2.2.3. Conclusion
2.3. Constant footprint and height comparison using TCAD simulation
2.3.1. Comparison guidelines
2.3.2. Results and discussion
2.3.3. Towards stacked nanosheets?
2.4. Internal spacer and gate alignment is key to reduce parasitic capacitances
2.5. Discussions
2.6. Conclusion
3. Stacked nanowire FETs: integration challenges and process optimization.
3.1. Gate last integration flows of stacked nanowires
3.1.1. NW Last: polysilicon sacrificial gate
3.1.2. NW First: HSQ sacrificial gate
3.1.3. Alternatives?
3.1.4. Conclusion
3.2. Si/SiGe superlattice
3.3. Si/SiGe fins patterning
3.4. SiGe selective removal
3.5. Source and drains (S/D) and internal spacers fabrication
3.5.1. Surface preparation
3.5.2. Selective epitaxial growth (SEG)
3.5.3. S/D in a NW last approach with aligned internal spacers.
3.5.4. S/D in a NW first approach with self-aligned internal spacers
3.6. Electron beam lithography of HSQ
3.6.1. Conditions
3.6.2. Layouts description
3.6.3. Resist developing
3.6.4. Observations
3.6.5. Limitation and perspectives
3.7. Chemical mechanical planarization (CMP)
3.7.1. Introduction to CMP
3.7.2. Polysilicon sacrificial gate CMP (NW Last approach)
3.7.3. Sacrificial gate opening CMP
3.7.4. Metal CMP (NW Last & NW First)
3.8. Conclusion
4. Achieved integrations and optimization perspectives
4.1. Electrical characterization of SNWFETs fabricated in a NW last approach
4.1.1. Device fabrication
4.1.2. Electrical measurements
4.2. 3D SAC and STI: HSQ the ultimate resist?
4.2.1. SNWFETs fabricated in a NW first approach
4.2.2. Alternative approach with HSQ sacrificial gates and lateral insulation
General Conclusion
