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Table of contents
1 Introduction
1.1 Area of focus
1.1.1 Clocking in large digital circuits
1.1.2 Clock error issues
1.2 State of the art: synchronous clocking in modern SoC
1.2.1 Conventional clock trees
1.2.2 Optical distribution technique
1.2.3 Multioscillator architectures
1.2.4 Synchronous clocking architectures: conclusion
1.3 Thesis outline and contribution
2 Network of distributed ADPLLs
2.1 Introduction
2.2 Proposed clocking architecture
2.2.1 Network of coupled PLLs
2.2.2 Digital phase synthesis
2.2.3 Blocks of the ADPLL network
2.2.4 Specification of clocking network parameters
2.3 Multiplicity of synchronisation modes
2.3.1 Definition of the problem
2.3.2 Synchronization mode selection
2.4 Stability of the PLL networks
2.5 Modeling of the clocking network
2.5.1 The model of the phase comparator
2.5.2 Loop filter
2.5.3 DCO
2.5.4 Simulation of ADPLL
2.5.5 Simulation of network
2.6 Conclusion
3 Digitally controlled oscillator design
3.1 Introduction
3.2 Digital frequency tuning in ring oscillators
3.2.1 Capacitive tuning
3.2.2 Current/Voltage tuning
3.2.3 Current tuning with width modulation technique
3.2.4 Frequency tuning in 2D array oscillator
3.2.5 The choice of the coding
3.3 DCO architecture
3.3.1 Oscillator topology
3.3.2 Control algorithm
3.4 Sizing of the DCO core and tuning cells
3.5 VHDL modeling of the oscillator
3.5.1 Precise modeling of the real code-frequency characteristic
3.5.2 Synthesis of the DCO output frequency in the precise VHDL model
3.6 DCO layout desing I: the DCO floorplan
3.6.1 Cell based design
3.6.2 Power planning
3.6.3 Signal flow oriented layout
3.6.4 Guard rings
3.6.5 General DCO floorplan
3.7 DCO layout design II: cell design
3.7.1 Main inverters
3.7.2 Feedback wire and decoupling capacitors
3.7.3 Tuning inverters
3.7.4 DCO output interface
3.7.5 A, B and C bus generator
3.7.6 DCO chip
3.8 DCO chip test
3.8.1 Impact of the supply variations
3.8.2 Chip-to-chip variations
3.8.3 Power consumption
3.8.4 Linearity
3.8.5 Jitter characteristics
3.9 Conclusion
4 Digital blocks of the ADPLL
4.1 Introduction
4.2 Digital phase/frequency error measurement
4.2.1 Digital versus analog phase comparators
4.2.2 Phase comparators versus phase-frequency detectors
4.2.3 The digital PFD architecture
4.2.4 Metastability problem
4.3 Implementation of digital PFD
4.3.1 Bang-bang detector implementation
4.3.2 Time-to-digital converter
4.3.3 Implementation of PFD
4.4 Digital loop control of ADPLL network node
4.4.1 Error combining block
4.4.2 PI filter
4.4.3 Implementation
4.4.4 ADPLL simulation results
4.5 Node programming mechanism
4.6 Conclusion
5 Clock network implementation
5.1 Introduction
5.2 FPGA prototyping
5.2.1 Synthesizable DCO
5.2.2 FPGA based TDC
5.2.3 Experimental results
5.2.4 FPGA prototyping: conclusion
5.3 Silicon implementation of the clock network
5.3.1 Floorplan of the test chip
5.3.2 Design for test
5.3.3 Test chip layout
5.4 Measurement results
5.4.1 Initial frequencies of DCOs
5.4.2 Supply voltage sensivity
5.4.3 Power consumption
5.4.4 Bidirectional configuration
5.4.5 Unidirectional configuration
5.4.6 Corner to corner timing errors
5.4.7 Study of mode-locking phenomenon
5.4.8 Coefficient variation
5.5 Conclusion
6 Conclusion and Perspectives
6.1 Thesis summary and conclusions
6.2 Future work
Appendices
A VHDL models of the ADPLL blocks
B Phase error sign detection theorem proof
C Matlab scripts
D DCO test chip characterization flow
E FPGA prototyping of the clocking network
G Clocking network test chip characterization flow
Bibliography
