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Table of contents
1 Introduction
1.1 Evolution of Video Technology
1.1.1 The Continuous Video Picture
1.2 Analog and Digital Video Data
1.2.1 Color Spaces
1.2.2 Analog Video Transmission
1.2.3 Y′C′
1.3 The Video Signal Composition
1.3.1 Synchronization Pulses
1.3.2 Sync-Tip
1.3.3 Front and Back Porch
1.3.4 Color Burst
1.3.5 Breezeway
1.3.6 Blanking Interval
1.3.7 Blanking and Black Level
1.3.8 Clamp
1.3.9 Chroma Signal
1.3.10 Luma Signal
1.3.11 Color Saturation
1.4 Requirements on Popular Video Standards
2 Video Analog Front Ends
2.1 The High Speed Video IC Architecture
2.1.1 Time-Reference Channel
2.1.2 Digitizing Channel
2.1.3 Signal Chain of the Video Digitizing Channel
2.1.4 AC Coupling
2.1.5 Clamping and DC Restoration
2.1.6 Anti Aliasing Filter
2.1.7 Type of Filter
2.1.8 Split Filter Architecture and Digital Tuning
2.2 ADC
2.3 Programmable Gain Amplifier
2.3.1 Revisited PGA Architecture due to CMOS Process Limitations
2.3.2 PGA Specifications
2.3.3 Linearity and Noise
2.3.4 Slew Rate
2.3.5 Bandwidth
2.3.6 Leakage
2.4 On Screen Artifacts due to Errors in Video AFE
2.4.1 Effect of Flicker Noise
2.4.2 ADC Errors
2.4.3 Timing Errors
2.4.4 Leakage
3 OTA Architecture
3.1 A Pseudo Differential OTA and Common Mode Feedforward Technique
3.2 Common Mode Feedback using Cascaded OTA Structures
3.3 Frequency Response
3.3.1 Cascaded OTA structures and Compensation
3.4 Noise and OTA Nonlinearity
3.4.1 Noise vs. Speed vs. Linearity
4 Behavior Level Video PGA Modeling
4.1 Resistor Emulation by Switched Capacitor Circuits
4.1.1 Switches in Signal Path
4.2 Analysis of Switch Capacitor PGA Switching Scheme
4.3 Oversampling in Video PGAs
4.4 Noise Considerations and Minimum Size of Capacitor
4.5 Developing a Higher Level OTA Model
4.5.1 Single Pole OTA Model
4.5.2 Enhanced OTA Simulation Model
4.5.3 The Current Limiting Model
4.5.4 Designing Enhanced OTA Model
4.6 Modeling a Switched Capacitor Video PGA
4.7 Sync-Tip Compensation – an SC Level Shifter
4.8 Simulation Testbench of the PGA Switching Scheme
5 Transistor Level Design
5.0.1 Modern Trends in Low Voltage Analog Design
5.1 The 65 nm CMOS Process
5.2 OTA Design in 65 nm CMOS
5.2.1 Design of OTA with CMFF
5.2.2 Achieved Specifications for OTA (with CMFF only)
5.2.3 Designing the OTA Structure with CMFB Devices
5.3 Cascading OTA Structures
5.4 Nested Miller Compensation
5.4.1 Reducing Output Capacitance
5.4.2 Standard Expressions – Unreliable
5.5 Noise Analysis
5.6 Non-Linearity and Distortion
5.7 Bandwidth vs. Stability
5.8 Final OTA Specifications
6 Conclusions and Future Work
Bibliography
A MATLAB Codes
B Skill Scripts
B.1 Pole and Zero Locations
B.2 Harmonic Distortion
