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Table of contents
1 Introduction
1.1 Motivation
1.1.1 System Overview
1.2 Emulator Requirements
1.3 Design Specifications
1.3.1 Existing Architectures
1.3.2 Design Parameters
1.4 Thesis Organization
2 Generic Model for Power Electronic Systems
2.1 Design Considerations
2.1.1 State Space Representation
2.1.2 Linearity
2.1.3 Discrete Time
2.2 Example Systems
2.2.1 Multi-Phase DC-DC Converter
2.2.2 Three phase Induction Motor Drive
2.3 Linear Parameter Varying Systems
2.3.1 Discretization
3 Firmware Architecture
3.1 Functional Overview
3.2 Digital HW Platform
3.3 Soft-Core Processor
3.3.1 IP Selection
3.3.2 SoC Configuration
3.3.3 WB Slave Interface with Custom Logic Blocks
3.4 Analog-to-Digital Converter Emulation
3.4.1 Specifications
3.4.2 SPI Master
3.4.3 SPI Slave
4 State Calculation Logic
4.1 Matrix-Vector Multiplication
4.2 Decomposition of the System Matrices
4.3 Module Design
4.3.1 Processing Element
4.3.2 PE Integration
4.3.3 FSM Design
4.4 Fixed Point Arithmetic
5 Hardware Validation
5.1 Testing Environment
5.1.1 Multi-phase DC-DC Converter : Model
5.1.2 Hardware Setup
5.1.3 PWM Signal
5.2 Waveform Comparison
6 Implementation Results
6.1 Maximum Clock Frequency
6.2 Scalability
6.3 Example System: Sampling Rate and Resource Usage
6.4 Numerical Error
7 Conclusion
7.0.1 Future Work
Bibliography
A Appendix: LatticeMico32 Processor Configuration
A.1 Introduction
A.2 Integrating a LM32 based SoC with Xilinx tools
A.2.1 Steps for Integration with Xilinx Tools
A.2.2 Using Block RAM for Code/Data memory
A.2.3 Using Xilinx data2mem Utility to update bitfile with Software Executable
B Appendix: Data Sheet References
B.1 Slice Architecture: Xilinx DSP48A1 Slice for Spartan6 FPGA Family
B.2 SPI Interface Timing Diagram
C Appendix: HDL Code Snippets
C.1 Dual Port Block Memory with Generic Bus-Width
C.2 Generic Depth Moving Average Filter for Binary Inputs
