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Table of contents
1 introduction
1.1 Preface
1.1.1 AI Hardware Accelerators
1.1.2 Neuromorphic Computing
1.1.3 Is AI Hardware Fault-Tolerant?
1.2 Motivation
1.3 Methodology
1.3.1 Fault Injection
1.3.2 Fault Modeling
1.3.3 Fault Tolerance
1.4 Thesis Structure
2 spiking neural networks & their fault tolerance: a literature review
2.1 Spiking Neural Networks
2.1.1 The Spiking Neuron
2.1.1.1 The Spike
2.1.1.2 The Membrane Potential
2.1.1.3 Spike Generation
2.1.2 Neural Coding Schemes
2.2 Spiking Neural Networks in Hardware
2.2.1 Neuron Models
2.2.2 Address Event Representation
2.3 Neuromorphic Technology Prospects and Challenges
2.4 State-of-the-Art in Testing and Fault Tolerance in Hardware Neural Networks
2.4.1 Fault, Error, and Failure
2.4.2 Fault Injection in the Literature
2.4.3 Fault Tolerance in the Literature
3 a self-testing analog spiking-neuron circuit
3.1 A Biological Perspective
3.2 The Biologically-Inspired Neuron Circuit
3.2.1 The Mathematical Model
3.2.2 The Neuron Circuit
3.3 The Built-In Self-Test
3.3.1 BIST Architecture
3.3.2 Expected BIST Response
3.3.3 BIST Verification
3.4 Results and Discussion
4 hardware-level fault modeling
4.1 Fault Simulation Framework
4.2 The Spiking Neuron
4.2.1 Behavioral Model
4.2.2 Transistor-Level Design
4.3 Spiking Neuron Faulty Behaviors
4.3.1 Catastrophic Faults
4.3.2 Parametric Faults
4.4 Behavioral-level Fault Model
5 fault injection and resiliency analysis in spiking neural networks
5.1 Fault Models
5.1.1 Neuron Fault Models
5.1.2 Synapse Fault Models
5.2 Case Studies
5.2.1 The Spike Response Model
5.2.2 Case Study (1): The N-MNIST SNN
5.2.2.1 The N-MNIST Dataset
5.2.2.2 The N-MNIST SNN Architecture
5.2.3 Case Study (2): The DVS-gesture SNN
5.2.3.1 The DVS-gesture Dataset
5.2.3.2 The DVS-gesture SNN Architecture
5.3 Fault Modeling & Injection Methodology
5.4 Fault Injection Experiments & Results: (1) The N-MNIST SNN
5.4.1 Neuron Faults
5.4.1.1 Dead Neuron Faults
5.4.1.2 Saturated Neuron Faults
5.4.1.3 Parametric Faults
5.4.2 Synapse Faults
5.4.2.1 Dead Synapse Faults
5.4.2.2 Saturated Synapse Faults
5.5 Fault Injection Experiments & Results: (2) The DVS-gesture SNN
5.5.1 Neuron Faults
5.5.1.1 Dead Neuron Faults
5.5.1.2 Saturated Neuron Faults
5.5.1.3 Parametric Faults
5.6 Discussion
6 neuron fault tolerance
6.1 Passive Fault Tolerance Strategy
6.1.1 Training with Dropout
6.1.2 SNN Tolerance to Multiple Faults
6.2 Active Fault Tolerance Strategy
6.2.1 Active Fault Tolerance in the Output Layer
6.2.2 Active Fault Tolerance in the Hidden Layers
6.2.2.1 Offline Self-Test
6.2.2.2 Online Self-Test
6.2.2.3 Recovery Mechanisms
7 a spiking neural network hardware implementation
7.1 The Convolutional Node
7.1.1 The Convolutional Unit
7.1.1.1 Unit Parameters
7.1.1.2 The Convolution Operation
7.1.1.3 Global Leakage
7.1.1.4 Rate Saturation Mechanism
7.1.1.5 Output Event Generation & Traffic Control
7.1.2 The Router
7.1.3 The Configuration Block
7.2 The Experiment
7.2.1 The Poker-Card Symbols Dataset
7.2.2 The Convolutional SNN
7.2.3 The Experimental Setup & Results
7.3 Putting the Hardware in the Loop
8 conclusions
8.1 Thesis Contributions
8.2 Future Perspectives
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